IPR-QDRII/UNI Altera, IPR-QDRII/UNI Datasheet - Page 37

• Manufacturer Part Number: IPR-QDRII/UNI
• Description: IP CORE Renewal Of IP-QDRII/UNI
• Manufacturer: Altera

Specifications of IPR-QDRII/UNI

• Software Application: IP CORE, Memory Controllers, SRAM
• Supported Families: Arria II GX, HardCopy III, Stratix III, Stratix IV
• Core Architecture: FPGA
• Core Sub-architecture: Arria, HardCopy, Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: na

Block Description
December 2010 Altera Corporation
Avalon-MM Slave Read and Write Interfaces
Command Issuing FSM
The controller translates memory requests from the Avalon Memory-Mapped
(Avalon-MM) interface to AFI, while satisfying timing requirements imposed by the
memory configurations. QDR II and QDR II+ SRAM has unidirectional data buses,
therefore read and write operations are highly independent of each other and each
has its own interface and state machine.
This topic describes the blocks in the IP.
QDR II and QDR II+ SRAM controller architecture.
Figure 5–1. QDR II and QDR II+ SRAM Controller Architecture Block Diagram
The read and write blocks accept from the Avalon-MM interface read and write
requests respectively. Each block has a simple state machine that represents the state
of the command and address registers, which stores the command and address when
a request arrives.
The read data passes through without the controller registering it, as the PHY takes
care of read latency. The write data goes through a pipeline stage to delay for a fixed
number of cycles as specified by the write latency. In the full-rate burst length of four
controller, the write data is also multiplexed into a burst of 2, which is then
multiplexed again in the PHY to become a burst of 4 in DDR.
The user interface to the controller has separate read and write Avalon-MM interfaces
because reads and writes are independent of each other in the memory device. The
separate channels give efficient use of available bandwidth.
The command-issuing full-state machine (FSM) has two states: INIT and
INIT_COMPLETE. In the INIT_COMPLETE state, commands are issued immediately as
requests arrive using combinational logic and do not require state transitions.
AFI
5. Functional Description—Controller
Section III. QDR II and QDR II+ SRAM Controller with UniPHY User Guide
with UniPHY
Controller
Command
Issuing
Write
FIFO
Data
FSM
Figure 5–1
shows a block diagram of the
External Memory Interface Handbook Volume 3
Avalon-MM Slave
Write Interface
Avalon-MM Slave
Write Interface
Avalon-MM Slave
Read Interface