IPR-QDRII/UNI Altera, IPR-QDRII/UNI Datasheet - Page 51

• Manufacturer Part Number: IPR-QDRII/UNI
• Description: IP CORE Renewal Of IP-QDRII/UNI
• Manufacturer: Altera

Specifications of IPR-QDRII/UNI

• Software Application: IP CORE, Memory Controllers, SRAM
• Supported Families: Arria II GX, HardCopy III, Stratix III, Stratix IV
• Core Architecture: FPGA
• Core Sub-architecture: Arria, HardCopy, Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: na

Chapter 6: Functional Description—UniPHY
UniPHY Signals
Table 6–5. AFI Signals (Part 2 of 2)
Table 6–6. QDR II and QDR II+ SRAM Interface Signals
December 2010 Altera Corporation
Address and Command
afi_addr
afi_wps_n
afi_rps_n
Write Data
afi_dm
afi_wdata
afi_wdata_valid
Read Data
afi_rdata
afi_rdata_en
afi_rdata_valid
Calibration Control and Status
afi_cal_success
afi_cal_fail
mem_address
mem_bws_n
mem_wps_n
mem_rps_n
mem_doff_n
Name
Name
Table 6–6
shows the QDR II and QDR II+ SRAM interface signals.
Input
Input
Input
Output
Output
Input
Input
Input
Output
Input
Output
Output
Output
Output
Output
Output
Output
Output
Direction
Direction
MEM_ADDRESS_WIDTH
2 x MEM_ADDRESS_WIDTH
2 x MEM_ADDRESS_WIDTH
MEM_CONTROL_WIDTH
MEM_CONTROL_WIDTH
MEM_DM_WIDTH ×
AFI_RATIO
MEM_DQ_WIDTH × 2 ×
AFI_RATIO
MEM_WRITE_DQS_
WIDTH × AFI_RATIO
MEM_DQ_WIDTH × 2 ×
AFI_RATIO
MEM_READ_DQS_
WIDTH × AFI_RATIO
AFI_RATIO
1
1
MEM_ADDRESS_WIDTH
MEM_DM_WIDTH
MEM_CONTROL_WIDTH
MEM_CONTROL_WIDTH
MEM_CONTROL_WIDTH
Width
Width
Section III. QDR II and QDR II+ SRAM Controller with UniPHY User Guide
For full-rate, burst-of-4 configuration.
For full-rate, burst-of-2 configuration. The
upper memory address bits contain the
write address, while the lower memory
address bits contain the read address.
For half-rate, burst-of-4 configuration. The
upper memory address bits contain the read
address, while the lower memory address
bits contain the write address.
Write enable.
Read enable.
Data mask input that generates mem_dm.
Write data input that generates mem_dq.
Write data valid that generates mem_dq and
mem_dm output enables.
Read data
Doing read input. Indicates that the memory
controller is currently performing a read
operation.
Read data valid indicating valid read data on
afi_rdata, in the byte lanes and
alignments that were indicated on
afi_rdata_en.
‘1’ signals that calibration has completed
‘1’ signals that calibration has failed
Address.
Data mask.
Write enable.
Read enable.
Connecting this pin to ground turns off the
DLL inside the device.
External Memory Interface Handbook Volume 3
Description
Description
6–11