IPR-QDRII/UNI Altera, IPR-QDRII/UNI Datasheet - Page 52

• Manufacturer Part Number: IPR-QDRII/UNI
• Description: IP CORE Renewal Of IP-QDRII/UNI
• Manufacturer: Altera

Specifications of IPR-QDRII/UNI

• Software Application: IP CORE, Memory Controllers, SRAM
• Supported Families: Arria II GX, HardCopy III, Stratix III, Stratix IV
• Core Architecture: FPGA
• Core Sub-architecture: Arria, HardCopy, Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: na

6–12
Table 6–6. QDR II and QDR II+ SRAM Interface Signals
Table 6–7. Top-Level HardCopy Migration Signals (Part 1 of 2)
External Memory Interface Handbook Volume 3
Section III. QDR II and QDR II+ SRAM Controller with UniPHY User Guide
mem_k, mem_kn
mem_cq, mem_cq_n
mem_d
mem_q
altsyncram Signals
hc_rom_config_clock
hc_rom_config_datain
hc_rom_config_rom_data_ready
hc_rom_config_init
hc_rom_config_init_busy
hc_rom_config_rom_rden
hc_rom_config_rom_address
DLL Reconfiguration Signals
hc_dll_config_dll_offset_ctrl_addnsub
hc_dll_config_offset_ctrl_offset
hc_dll_config_dll_offset_ctrl_offsetctrlout
Name
Table 6–7
Name
shows the top-level signals generated for HardCopy migration.
Output
Input
Input
Output
Direction
MEM_WRITE_DQS_
WIDTH
MEM_READ_DQS_
WIDTH
MEM_DQ_WIDTH
MEM_DQ_WIDTH
Width
Input
Input
Input
Input
Output
Output
Output
Input
Input
Output
Direction
Write clock(s) to memory, 1 clock per DQS
group.
Read clock(s) from memory, 1 clock per
DQS group
Input data bus.
Output data bus.
Write clock for the ROM loader. This clock
is used as the write clock of the NIOS code
memory.
Data input from external ROM.
Asserts to the code memory loader that
the word memory is ready to be loaded.
Triggers the ROM loading process. Should
be asserted for one hc_rom_config_clock
cycle after PLL is locked
When asserted, indicates ROM loading is
in progress. The soft_reset_n signal
should be de-asserted if the ROM data is
not loaded, and also when the ROM is
being loaded. The falling edge of
hc_rom_config_init_busy indicates the
completion of the ROM loading process, at
which time, soft_reset_n can be asserted.
Read-enable signal that connects to the
external ROM.
ROM address that connects to the external
ROM.
Addition and subtraction control port for
the DLL. This port controls if the
delay-offset setting on hc_dll_config_
dll_offset_ctrl_offset is added or
subtracted.
Offset input setting for the DLL. This
setting is a Gray-coded offset that is added
or subtracted from the current value of the
DLL’s delay chain.
The registered and Gray-coded value of the
current delay-offset setting.
Chapter 6: Functional Description—UniPHY
December 2010 Altera Corporation
Description
Description
UniPHY Signals