IPR-QDRII/UNI Altera, IPR-QDRII/UNI Datasheet - Page 44

• Manufacturer Part Number: IPR-QDRII/UNI
• Description: IP CORE Renewal Of IP-QDRII/UNI
• Manufacturer: Altera

Specifications of IPR-QDRII/UNI

• Software Application: IP CORE, Memory Controllers, SRAM
• Supported Families: Arria II GX, HardCopy III, Stratix III, Stratix IV
• Core Architecture: FPGA
• Core Sub-architecture: Arria, HardCopy, Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: na

6–4
Figure 6–3. Write Datapath
External Memory Interface Handbook Volume 3
Section III. QDR II and QDR II+ SRAM Controller with UniPHY User Guide
Kn
K
Write Datapath
Read Datapath
D[n-1]
D[0]
ALTIOBUF
The write datapath passes write data from the memory controller to the I/O. The
QDR II interface has separate unidirectional read and write pins. The write pins are
not controlled by the output-enable signal, and are always driven. Because the pins
are unidirectional, there is no need for dynamic termination control.
Figure 6–3
is sent to a DDIO_OUT cell. The output of ALTDQ_DQS feeds an ALTIOBUF buffer
which creates a pair of pseudodifferential clocks that connects to the memory. In
full-rate mode, only the SDR-DDR portion of the ALTDQ_DQS logic is used; in
half-rate mode, the HDR-SDR circuitry is also required. The
<variation_name>_pin_assignments.tcl script automatically specifies the logic option
that associates all DQ pins to the DQS pin. The Fitter treats the pins as a DQS/DQ pin
group.
The read data is captured in the input mode ALTDQ_DQS in the I/O. The captured
data is then forwarded to the read datapath. The read datapath synchronizes read
data from the read capture clock domain to the AFI clock domain and converts data
from SDR to HDR (half-rate designs only).
ALTDQ_DQS
SDR
DDIO_OUT
DDR
illustrates the write datapath. The full-rate PLL output clock phy_mem_clk
DDIO_OUT
DDIO_OUT
0
n-1
HDR
SDR
DDIO_OUT
DDIO_OUT
DDIO_OUT
DDIO_OUT
2n-2
2n-1
1
0
Chapter 6: Functional Description—UniPHY
December 2010 Altera Corporation
wdata[4n-4]
wdata[4n-3]
wdata[4n-2]
wdata[4n-1]
wdata[1]
wdata[2]
wdata[3]
wdata[0]
vcc
phy_afi_clk
phy_mem_write_clk
phy_mem_clk
gnd
wdata[4n-1:0]
Block Description