IPR-QDRII/UNI Altera, IPR-QDRII/UNI Datasheet - Page 41

• Manufacturer Part Number: IPR-QDRII/UNI
• Description: IP CORE Renewal Of IP-QDRII/UNI
• Manufacturer: Altera

Specifications of IPR-QDRII/UNI

• Software Application: IP CORE, Memory Controllers, SRAM
• Supported Families: Arria II GX, HardCopy III, Stratix III, Stratix IV
• Core Architecture: FPGA
• Core Sub-architecture: Arria, HardCopy, Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: na

Block Description
December 2010 Altera Corporation
I/O Pads
This chapter describes the PHY part of the QDR II and QDR II+ SRAM controllers
with UniPHY.
The PHY comprises the following major functional units:
■
■
■
■
■
Figure 6–1
Figure 6–1. PHY Block Diagram
The I/O pads contain all the I/O instantiations. The bulk of the UniPHY I/O circuitry
is encapsulated in the ALTDQ_DQS megafunction (ALTDQ_DQS2 for Stratix V series
devices).
Reset and Clock Generation
Address and Command Datapath
Write Datapath
Read Datapath
Sequencer
External
Memory
Device
shows the PHY block diagram.
I/O Pads
6. Functional Description—UniPHY
Section III. QDR II and QDR II+ SRAM Controller with UniPHY User Guide
UniPHY
Command
Generation
Datapath
Address
Datapath
Datapath
Write
Read
Reset
and
FPGA
External Memory Interface Handbook Volume 3
Sequencer
Controller
Memory
AFI to
Controller
Memory