IPR-QDRII/UNI Altera, IPR-QDRII/UNI Datasheet - Page 33

• Manufacturer Part Number: IPR-QDRII/UNI
• Description: IP CORE Renewal Of IP-QDRII/UNI
• Manufacturer: Altera

Specifications of IPR-QDRII/UNI

• Software Application: IP CORE, Memory Controllers, SRAM
• Supported Families: Arria II GX, HardCopy III, Stratix III, Stratix IV
• Core Architecture: FPGA
• Core Sub-architecture: Arria, HardCopy, Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: na

Chapter 3: Parameter Settings
Board Settings
December 2010 Altera Corporation
Table 3–8. Board Skews Settings (Part 2 of 2) (Part 2 of 2)
Maximun skew within
address/command bus
Average delay difference between
address/command and K
Average delay difference between
write data signals and K
Average delay difference between
read data signals and CQ
Parameter
Section III. QDR II and QDR II+ SRAM Controller with UniPHY User Guide
The maximum skew between the address/command
signals.
A value equal to the average of the longest and smallest
address/command signal delay values, minus the delay of
the K signal. The value can be positive or negative.
A value equal to the average of the longest and smallest
write data signal delay values, minus the delay of the K
signal. Write data signals include the D and BWS signals.
The value can be positive or negative.
A value equal to the average of the longest and smallest
read data signal delay values, minus the delay of the CQ
signal. The value can be positive or negative.
External Memory Interface Handbook Volume 3
Description
3–5