AD9516-5BCPZ-REEL7 Analog Devices Inc, AD9516-5BCPZ-REEL7 Datasheet - Page 28

• Manufacturer Part Number: AD9516-5BCPZ-REEL7
• Description: 10/14 Chan Clock IC W/PLL-no VCO
• Manufacturer: Analog Devices Inc
• Type: Clock Generator, Fanout Distributionr

Specifications of AD9516-5BCPZ-REEL7

• Pll: Yes
• Input: CMOS, LVDS, LVPECL
• Output: CMOS, LVDS, LVPECL
• Number Of Circuits: 1
• Ratio - Input:output: 1:14
• Differential - Input:output: Yes/Yes
• Frequency - Max: 2.4GHz
• Divider/multiplier: Yes/No
• Voltage - Supply: 3.135 V ~ 3.465 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 64-LFCSP
• Frequency-max: 2.4GHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

AD9516-5
Phase-Locked Loop (PLL)
The AD9516 includes on-chip PLL blocks that can be used with
an external VCO or VCXO to create a complete phase-locked
loop. The PLL requires an external loop filter, which usually
consists of a small number of capacitors and resistors. The
configuration and components of the loop filter help to establish
the loop bandwidth and stability of the PLL.
The AD9516 PLL is useful for generating clock frequencies from a
supplied reference frequency. This includes conversion of reference
frequencies to much higher frequencies for subsequent division
and distribution. In addition, the PLL can be used to clean up
jitter and phase noise on a noisy reference. The exact choice of
PLL parameters and loop dynamics is application specific. The
flexibility and depth of the AD9516 PLL allow the part to be
tailored to function in many different applications and signal
environments.
Configuration of the PLL
Configuration of the PLL is accomplished by programming
the various settings for the R divider, N divider, PFD polarity,
and charge pump current. The combination of these settings
determines the PLL loop bandwidth. These are managed through
programmable register settings and by the design of the external
loop filter.
Successful PLL operation and satisfactory PLL loop performance
are highly dependent on proper configuration of the PLL settings,
and the design of the external loop filter is crucial to the proper
operation of the PLL.
REFIN (REF1)
REFIN (REF2)
CLK
CLK
REF1
REF2
REF_SEL
SWITCHOVER
REFERENCE
STATUS
STATUS
1
2, 3, 4, 5, OR 6
DIVIDE BY
VS
PRESCALER
0
P, P + 1
GND
N DIVIDER
RSET
DIST
COUNTERS
REF
Figure 34. PLL Functional Block Diagram
R DIVIDER
A/B
Rev. 0 | Page 28 of 76
0
1
VCO STATUS
REFMON
PROGRAMMABLE
PROGRAMMABLE
R DELAY
N DELAY
ADIsimCLK™ is a free program that can help with the design
and exploration of the capabilities and features of the AD9516,
including the design of the PLL loop filter. ADIsimCLK Version 1.2
(or later) can be used for modeling the AD9516 loop filter. It is
available at www.analog.com/clocks.
Phase Frequency Detector (PFD)
The PFD takes inputs from the R divider and N divider and
produces an output proportional to the phase and frequency
difference between them. The PFD includes a programmable
delay element that controls the width of the antibacklash pulse.
This pulse ensures that there is no dead zone in the PFD transfer
function and minimizes phase noise and reference spurs. The
antibacklash pulse width is set by 0x017[1:0].
An important limit to keep in mind is the maximum frequency
allowed into the PFD. The maximum input frequency into the
PFD is a function of the antibacklash pulse setting, as specified
in Table 2, Phase/Frequency Detector (PFD) parameter.
FREQUENCY
DETECTOR
DETECT
LOCK
PHASE
CPRSET
PLL
REF
CHARGE PUMP
VCP
HOLD
LD
CP
STATUS