AD9516-5BCPZ-REEL7 Analog Devices Inc, AD9516-5BCPZ-REEL7 Datasheet - Page 68

• Manufacturer Part Number: AD9516-5BCPZ-REEL7
• Description: 10/14 Chan Clock IC W/PLL-no VCO
• Manufacturer: Analog Devices Inc
• Type: Clock Generator, Fanout Distributionr

Specifications of AD9516-5BCPZ-REEL7

• Pll: Yes
• Input: CMOS, LVDS, LVPECL
• Output: CMOS, LVDS, LVPECL
• Number Of Circuits: 1
• Ratio - Input:output: 1:14
• Differential - Input:output: Yes/Yes
• Frequency - Max: 2.4GHz
• Divider/multiplier: Yes/No
• Voltage - Supply: 3.135 V ~ 3.465 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 64-LFCSP
• Frequency-max: 2.4GHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Reg.
Addr
(Hex) Bit(s) Name
190
190
191
191
191
191
191
192
192
193
193
194
194
Reg.
Addr
(Hex) Bit(s) Name
143
143
AD9516-5
Table 53. LVPECL Channel Dividers
[7:4]
[3:0]
[7]
[6]
[5]
[4]
[3:0]
[1]
[0]
[7:4]
[3:0]
[7]
[6]
[2:1] OUT9 LVDS output current
[0]
OUT9 power-down
Divider 0 low cycles
Divider 0 high cycles
Divider 0 bypass
Divider 0 nosync
Divider 0 force high
Divider 0 start high
Divider 0 phase offset
Divider 0 direct to output
Divider 0 DCCOFF
Divider 1 low cycles
Divider 1 high cycles
Divider 1 bypass
Divider 1 nosync
Description
Number of clock cycles (minus 1) of the Divider 0 input during which the Divider 0 output
stays low. A value of 0x7 means the divider is low for eight input clock cycles (default: 0x0).
Number of clock cycles (minus 1) of the Divider 0 input during which the Divider 0 output
stays high. A value of 0x7 means the divider is low for eight input clock cycles (default: 0x0).
Bypass and power-down the divider; route input to divider output.
[7] = 0; use divider.
[7] = 1; bypass divider (default).
Nosync.
[6] = 0; obey chip-level SYNC signal (default).
[6] = 1; ignore chip-level SYNC signal.
Force divider output to high. This requires that nosync also be set.
[5] = 0; divider output forced to low (default).
[5] = 1; divider output forced to high.
Selects clock output to start high or start low.
[4] = 0; start low (default).
[4] = 1; start high.
Phase offset (default: 0x0).
Connect OUT0 and OUT1 to Divider 0 or directly to CLK input.
[1] = 0: OUT0 and OUT1 are connected to Divider 0 (default).
[1] = 1;
If 0x1E1[0] = 0, the CLK is routed directly to OUT0 and OUT1.
If 0x1E1[0] = 1, there is no effect.
Duty-cycle correction function.
[0] = 0; enable duty-cycle correction (default).
[0] = 1; disable duty-cycle correction.
Number of clock cycles (minus 1) of the Divider 1 input during which the Divider 1 output stays
low. A value of 0x7 means the divider is low for eight input clock cycles (default: 0xB).
Number of clock cycles (minus 1) of the Divider 1 input during which the Divider 1 output stays
high. A value of 0x7 means the divider is low for eight input clock cycles (default: 0xB).
Bypass and power-down the divider; route input to divider output.
[7] = 0; use divider (default).
[7] = 1; bypass divider.
Nosync.
[6] = 0; obey chip-level SYNC signal (default).
[6] = 1; ignore chip-level SYNC signal.
Description
Set output current level in LVDS mode. This has no effect in CMOS mode.
[2] [1] Current (mA)
0
0
1
1
Power-down output (LVDS/CMOS).
[0] = 0; power on.
[0] = 1; power off (default).
0
1
0
1
1.75
3.5
5.25
7
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Recommended Termination (Ω)
100
100 (default)
50
50