AD9516-5BCPZ-REEL7 Analog Devices Inc, AD9516-5BCPZ-REEL7 Datasheet - Page 50

• Manufacturer Part Number: AD9516-5BCPZ-REEL7
• Description: 10/14 Chan Clock IC W/PLL-no VCO
• Manufacturer: Analog Devices Inc
• Type: Clock Generator, Fanout Distributionr

Specifications of AD9516-5BCPZ-REEL7

• Pll: Yes
• Input: CMOS, LVDS, LVPECL
• Output: CMOS, LVDS, LVPECL
• Number Of Circuits: 1
• Ratio - Input:output: 1:14
• Differential - Input:output: Yes/Yes
• Frequency - Max: 2.4GHz
• Divider/multiplier: Yes/No
• Voltage - Supply: 3.135 V ~ 3.465 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 64-LFCSP
• Frequency-max: 2.4GHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

AD9516-5
REGISTER MAP OVERVIEW
Register addresses that are not listed in Table 47 (as well as ones marked unused) are not used and writing to those registers has no effect.
The user should only write the default value to the register addresses marked reserved.
Table 47. Register Map Overview
Addr
(Hex)
Serial Port Configuration
000
001
002
to
003
004
PLL
010
011
012
013
014
015
016
017
018
019
01A
01B
01C
01D
01E
01F
020
to
04F
Parameter
Serial port
configuration
Read back
control
PFD and
charge pump
R Counter
A counter
B counter
PLL Control 1
PLL Control 2
PLL Control 3
PLL Control 4
PLL Control 5
PLL Control 6
PLL Control 7
PLL Control 8
PLL Control 9
PLL Readback
(read-only)
Bit 7
(MSB)
SDO
active
PFD
polarity
Set CP pin
to VCP/2
Unused
Unused
CLK
frequency
monitor
Disable
switchover
deglitch
R, A, B counters SYNC
pin reset
Unused
Unused
Unused
Bit 6
LSB first
Reset R
counter
Reference
frequency
monitor
threshold
REF2
( REFIN )
frequency
monitor
Select
REF2
Unused
Unused
Lock detect counter
Charge pump current
Holdover
Bit 5
Soft reset
Reset A and
B counters
REF1 (REFIN)
frequency
monitor
Use
REF_SEL pin
active
STATUS pin control
Rev. 0 | Page 50 of 76
Bit 4
Long
instruction
Reset all
counters
Digital lock
detect
window
Automatic
reference
switchover
PLL status
register
disable
REF2
selected
13-Bit B Counter Bits[7:0] (LSB)
R path delay
14-Bit R Divider Bits[7:0] (LSB)
Reserved (Read-only)
Unused
Unused
Unused
Unused
14-Bit R Divider Bits[13:8] (MSB)
Bit 3
Long
instruction
B counter
bypass
Disable
digital lock
detect
Stay on
REF2
LD pin
comparator
enable
CLK
frequency
> threshold
Charge pump mode
13-Bit B Counter Bits[12:8] (MSB)
6-Bit A counter
LD pin control
REFMON pin control
Bit 2
Soft reset
REF2
power on
Holdover
enable
REF2
frequency
> threshold
Bit 1
LSB first
REF1
power on
External
holdover
control
REF1
frequency
> threshold
N path delay
Prescaler P
Antibacklash pulse width
Reserved
PLL power-down
SDO active
Bit 0 (LSB)
Read back
active
registers
Differential
reference
Holdover
enable
Digital
lock
detect
Default
Value
(Hex)
18
00
7D
01
00
00
03
00
06
00
06
00
00
00
00
00
00
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