AD9516-5BCPZ-REEL7 Analog Devices Inc, AD9516-5BCPZ-REEL7 Datasheet - Page 29

• Manufacturer Part Number: AD9516-5BCPZ-REEL7
• Description: 10/14 Chan Clock IC W/PLL-no VCO
• Manufacturer: Analog Devices Inc
• Type: Clock Generator, Fanout Distributionr

Specifications of AD9516-5BCPZ-REEL7

• Pll: Yes
• Input: CMOS, LVDS, LVPECL
• Output: CMOS, LVDS, LVPECL
• Number Of Circuits: 1
• Ratio - Input:output: 1:14
• Differential - Input:output: Yes/Yes
• Frequency - Max: 2.4GHz
• Divider/multiplier: Yes/No
• Voltage - Supply: 3.135 V ~ 3.465 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 64-LFCSP
• Frequency-max: 2.4GHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Charge Pump (CP)
The charge pump is controlled by the PFD. The PFD monitors
the phase and frequency relationship between its two inputs, and
tells the CP to pump up or pump down to charge or discharge the
integrating node (part of the loop filter). The integrated and
filtered CP current is transformed into a voltage that drives the
tuning node of the external VCO to move the VCO frequency
up or down. The CP can be set (0x010[6:4]) for high impedance
(allows holdover operation), for normal operation (attempts to
lock the PLL loop), for pump-up, or for pump-down (test modes).
The CP current is programmable in eight steps from (nominally)
0.6 mA to 4.8 mA. The exact value of the CP current LSB is set
by the CPRSET resistor, which is nominally 5.1 kΩ. Doubling
the CPRSET resistor allows the charge pump current to be
programmed from (nominally) 0.3 mA to 2.4 mA
PLL External Loop Filter
An example of an external loop filter for a PLL is shown in
Figure 35. A loop filter must be calculated for each desired
PLL configuration. The values of the components depend on
the VCO frequency, the K
pump current, the desired loop bandwidth, and the desired
phase margin. The loop filter affects the phase noise, the
loop settling time, and the loop stability. A basic knowledge
of PLL theory is necessary for understanding loop filter design.
ADIsimCLK can help with the calculation of a loop filter
according to the application requirements.
PLL Reference Inputs
The AD9516 features a flexible PLL reference input circuit that
allows a fully differential input or two separate single-ended
inputs. The input frequency range for the reference inputs is
specified in Table 2. Both the differential and the single-ended
inputs are self-biased, allowing for easy ac coupling of input signals.
The differential input and the single-ended inputs share two
pins, REFIN (REF1) and REFIN (REF2). The desired reference
input type is selected and controlled by 0x01C (see
Table 49
When the differential reference input is selected, the self-bias
level of the two sides is offset slightly (see Table 2) to prevent
chattering of the input buffer when the reference is slow or missing.
The specification for this voltage level is found in Table 2. The
input hysteresis increases the voltage swing required of the
driver to overcome the offset.
).
Figure 35. Example of External Loop Filter for PLL
AD9516-5
CHARGE
PUMP
VCO
CLK/CLK
CP
, the PFD frequency, the charge
C1
EXTERNAL
VCO/VCXO
R1
C2
R2
C3
Table 47
and
Rev. 0 | Page 29 of 76
The single-ended inputs can be driven by either a dc-coupled
CMOS level signal or an ac-coupled sine wave or square wave.
Each single-ended input can be independently powered down
when not needed to increase isolation and reduce power. Either
a differential or a single-ended reference must be specifically
enabled. All PLL reference inputs are off by default.
The differential reference input is powered down whenever the
PLL is powered down, or when the differential reference input
is not selected. The single-ended buffers power down when the
PLL is powered down, and when their individual power-down
registers are set. When the differential mode is selected, the
single-ended inputs are powered down.
In differential mode, the reference input pins are internally self-
biased so that they can be ac-coupled via capacitors. It is possible to
dc couple to these inputs. If the differential REFIN is driven by a
single-ended signal, the unused side ( REFIN ) should be decoupled
via a suitable capacitor to a quiet ground.
equivalent circuit of REFIN.
Reference Switchover
The AD9516 supports dual single-ended CMOS inputs, as well
as a single differential reference input. In the dual single-ended
reference mode, the AD9516 supports automatic and manual
PLL reference clock switching between REF1 (on Pin REFIN)
and REF2 (on Pin REFIN ). This feature supports networking
and other applications that require redundant references. When
using reference switchover, the single-ended reference inputs
should be dc-coupled CMOS levels and never be allowed to
go to high impedance. If these inputs are allowed to go to high
impedance, noise may cause the buffer to chatter, causing a false
detection of the presence of a reference.
REFIN
REFIN
REF1
REF2
Figure 36. REFIN Equivalent Circuit
10kΩ
10kΩ
85kΩ
85kΩ
12kΩ
10kΩ
V
V
150Ω
150Ω
S
S
Figure 36
AD9516-5
shows the
V
S