AD9516-5BCPZ-REEL7 Analog Devices Inc, AD9516-5BCPZ-REEL7 Datasheet - Page 69

• Manufacturer Part Number: AD9516-5BCPZ-REEL7
• Description: 10/14 Chan Clock IC W/PLL-no VCO
• Manufacturer: Analog Devices Inc
• Type: Clock Generator, Fanout Distributionr

Specifications of AD9516-5BCPZ-REEL7

• Pll: Yes
• Input: CMOS, LVDS, LVPECL
• Output: CMOS, LVDS, LVPECL
• Number Of Circuits: 1
• Ratio - Input:output: 1:14
• Differential - Input:output: Yes/Yes
• Frequency - Max: 2.4GHz
• Divider/multiplier: Yes/No
• Voltage - Supply: 3.135 V ~ 3.465 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 64-LFCSP
• Frequency-max: 2.4GHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Reg.
Addr
(Hex) Bit(s) Name
194
194
194
195
195
196
196
197
197
197
197
197
198
198
Reg.
Addr
(Hex) Bit(s)
199
199
19A
19A
Table 54. LVDS/CMOS Channel Dividers
[5]
[4]
[3:0]
[1]
[0]
[7:4]
[3:0]
[7]
[6]
[5]
[4]
[3:0]
[1]
[0]
[7:4]
[3:0]
[7:4]
[3:0]
Divider 1 force high
Divider 1 start high
Divider 1 phase offset
Divider 1 direct to output
Divider 1 DCCOFF
Divider 2 low cycles
Divider 2 high cycles
Divider 2 bypass
Divider 2 nosync
Divider 2 force high
Divider 2 start high
Divider 2 phase offset
Divider 2 direct to output
Divider 2 DCCOFF
Name
Low Cycles Divider 3.1
High Cycles Divider 3.1
Phase Offset Divider 3.2
Phase Offset Divider 3.1
Description
Force divider output to high. This requires that nosync also be set.
[5] = 0; divider output forced to low (default).
[5] = 1; divider output forced to high.
Selects clock output to start high or start low.
[4] = 0; start low (default).
[4] = 1; start high.
Phase offset (default: 0x0).
Connect OUT2 and OUT3 to Divider 1 or directly to CLK input.
[1] = 0; OUT2 and OUT3 are connected to Divider 1 (default).
[1] = 1;
If 0x1E1[0] = 0, the CLK is routed directly to OUT2 and OUT3.
If 0x1E1[0] = 1, there is no effect.
Duty-cycle correction function.
[0] = 0; enable duty-cycle correction (default).
[0] = 1; disable duty-cycle correction.
Number of clock cycles (minus 1) of the Divider 2 input during which the Divider 2 output stays
low. A value of 0x7 means the divider is low for eight input clock cycles (default: 0x0).
Number of clock cycles (minus 1) of the Divider 2 input during which the Divider 2 output stays
high. A value of 0x7 means the divider is low for eight input clock cycles (default: 0x0).
Bypass and power down the divider; route input to divider output.
[7] = 0; use divider (default).
[7] = 1; bypass divider.
Nosync.
[6] = 0; obey chip-level SYNC signal (default).
[6] = 1; ignore chip-level SYNC signal.
Force divider output to high. This requires that nosync also be set.
[5] = 0; divider output forced to low (default).
[5] = 1; divider output forced to high.
Selects clock output to start high or start low.
[4] = 0; start low (default).
[4] = 1; start high.
Phase offset (default: 0x0).
Connect OUT4 and OUT5 to Divider 2 or directly to CLK input.
[1] = 0; OUT4 and OUT5 are connected to Divider 2 (default).
[1] = 1;
If 0x1E1[0] = 0, the CLK is routed directly to OUT4 and OUT5.
If 0x1E1[0] = 1, there is no effect.
Duty-cycle correction function.
[0] = 0; enable duty-cycle correction (default).
[0] = 1; disable duty-cycle correction.
Description
Number of clock cycles (minus 1) of the Divider 3.1 input during which the Divider 3.1 output
stays low. A value of 0x7 means the divider is low for eight input clock cycles (default: 0x2).
Number of clock cycles (minus 1) of the Divider 3.1 input during which the Divider 3.1 output
stays high. A value of 0x7 means the divider is low for eight input clock cycles (default: 0x2).
Refer to LVDSCMOS channel divider function description (default: 0x0).
Refer to LVDSCMOS channel divider function description (default: 0x0).
Rev. 0 | Page 69 of 76
AD9516-5