AD9516-5BCPZ-REEL7 Analog Devices Inc, AD9516-5BCPZ-REEL7 Datasheet - Page 37

• Manufacturer Part Number: AD9516-5BCPZ-REEL7
• Description: 10/14 Chan Clock IC W/PLL-no VCO
• Manufacturer: Analog Devices Inc
• Type: Clock Generator, Fanout Distributionr

Specifications of AD9516-5BCPZ-REEL7

• Pll: Yes
• Input: CMOS, LVDS, LVPECL
• Output: CMOS, LVDS, LVPECL
• Number Of Circuits: 1
• Ratio - Input:output: 1:14
• Differential - Input:output: Yes/Yes
• Frequency - Max: 2.4GHz
• Divider/multiplier: Yes/No
• Voltage - Supply: 3.135 V ~ 3.465 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 64-LFCSP
• Frequency-max: 2.4GHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Certain M and N values for a channel divider result in a non-
50% duty cycle. A non-50% duty cycle can also result with an
even division, if M ≠ N. The duty-cycle correction function
automatically corrects non-50% duty cycles at the channel
divider output to 50% duty cycle. Duty-cycle correction
requires the following channel divider conditions:
•
•
When not bypassed or corrected by the DCC function, the duty
cycle of each channel divider output is the numerical value of
(N + 1)/(N + M + 2) expressed as a %.
The duty cycle at the output of the channel divider for various
configurations is shown in Table 30 to Table 32.
Table 30. Duty Cycle with VCO Divider, Input Duty Cycle Is 50%
VCO
Divider
Even
Odd = 3
Odd = 5
Even, Odd
Even, Odd
Table 31. Duty Cycle with VCO Divider, Input Duty Cycle Is X%
VCO
Divider
Even
Odd = 3
Odd = 5
Even
Odd = 3
Odd = 3
Odd = 5
Odd = 5
An even division must be set as M = N
An odd division must be set as M = N + 1
N + M + 2
1 (divider
bypassed)
1 (divider
bypassed)
1 (divider
bypassed)
Even
Odd
Even
Odd
Even
Odd
N + M + 2
1 (divider
bypassed)
1 (divider
bypassed)
1 (divider
bypassed)
Even
Odd
D
X
D
X
DCCOFF = 1
50%
33.3%
40%
(N + 1)/
(N + M + 2)
(N + 1)/
(N + M + 2)
(N + 1)/
(N + M + 2)
(N + 1)/
(N + M + 2)
(N + 1)/
(N + M + 2)
(N + 1)/
(N + M + 2)
DCCOFF = 1
50%
33.3%
40%
(N + 1)/
(N + M + 2)
(N + 1)/
(N + M + 2)
Output Duty Cycle
Output Duty Cycle
DCCOFF = 0
50%
(1 + X%)/3
(2 + X%)/5
50%,
requires M = N
50%,
requires M = N + 1
50%,
requires M = N
(3N + 4 + X%)/(6N + 9),
requires M = N + 1
50%,
requires M = N
(5N + 7 + X%)/(10N + 15),
requires M = N + 1
DCCOFF = 0
50%
50%
50%
50%, requires M = N
50%, requires M = N + 1
Rev. 0 | Page 37 of 76
Table 32. Channel Divider Output Duty Cycle When the
VCO Divider Is Not Used
Input Clock
Duty Cycle
Any
Any
50%
X%
If the CLK input is routed directly to the output, the duty cycle of
the output is the same as the CLK input.
Phase Offset or Coarse Time Delay (0, 1, and 2)
Each channel divider allows for a phase offset, or a coarse time
delay, to be programmed by setting register bits (see Table 33).
These settings determine the number of cycles (successive
rising edges) of the channel divider input frequency by which to
offset, or delay, the rising edge of the output of the divider. This
delay is with respect to a nondelayed output (that is, with a
phase offset of zero). The amount of the delay is set by five bits
loaded into the phase offset (PO) register plus the start high
(SH) bit for each channel divider. When the start high bit is set,
the delay is also affected by the number of low cycles (M)
programmed for the divider.
It is necessary to use the SYNC function to make phase offsets
effective (see the Synchronizing the Outputs—SYNC Function
section).
Table 33. Setting Phase Offset and Division for Divider 0,
Divider 1, and Divider 2
Divider
0
1
2
Note that the value stored in the register equals the number of
cycles minus one. For example, 0x190[7:4] = 0001b equals two
low cycles (M = 2) for Divider 0.
Start
High (SH)
0x191[4]
0x194[4]
0x197[4]
N + M + 2
Channel
divider
bypassed
Even
Odd
Odd
D
X
Phase
Offset (PO)
0x191[3:0]
0x194[3:0]
0x197[3:0]
DCCOFF = 1
1 (divider
bypassed)
(N + 1)/
(M + N + 2)
(N + 1)/
(M + N + 2)
(N + 1)/
(M + N + 2)
Output Duty Cycle
Low Cycles
M
0x190[7:4]
0x193[7:4]
0x196[7:4]
DCCOFF = 0
Same as input
duty cycle
50%, requires M = N
50%, requires
M = N + 1
(N + 1 + X%)/(2 × N + 3),
requires M = N + 1
AD9516-5
High Cycles
N
0x190[3:0]
0x193[3:0]
0x196[3:0]