AD9516-5BCPZ-REEL7 Analog Devices Inc, AD9516-5BCPZ-REEL7 Datasheet - Page 31

• Manufacturer Part Number: AD9516-5BCPZ-REEL7
• Description: 10/14 Chan Clock IC W/PLL-no VCO
• Manufacturer: Analog Devices Inc
• Type: Clock Generator, Fanout Distributionr

Specifications of AD9516-5BCPZ-REEL7

• Pll: Yes
• Input: CMOS, LVDS, LVPECL
• Output: CMOS, LVDS, LVPECL
• Number Of Circuits: 1
• Ratio - Input:output: 1:14
• Differential - Input:output: Yes/Yes
• Frequency - Max: 2.4GHz
• Divider/multiplier: Yes/No
• Voltage - Supply: 3.135 V ~ 3.465 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 64-LFCSP
• Frequency-max: 2.4GHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Table 24. How a 10 MHz Reference Input May Be Locked to Any Integer Multiple of N
f
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
1
Digital Lock Detect (DLD)
By selecting the proper output through the mux on each pin, the
DLD function is available at the LD, STATUS, and REFMON pins.
The digital lock detect circuit indicates a lock when the time
difference of the rising edges at the PFD inputs is less than a
specified value (the lock threshold). The loss of a lock is indicated
when the time difference exceeds a specified value (the unlock
threshold). Note that the unlock threshold is wider than the
lock threshold, which allows some phase error in excess of the
lock window to occur without chattering on the lock indicator.
The lock detect window timing depends on the value of the
CPRSET resistor, as well as three settings: the digital lock detect
window bit (0x018[4]), the antibacklash pulse width bit
(0x017[1:0], see Table 2), and the lock detect counter
(0x018[6:5]). The lock and unlock detection values in Table 2
are for the nominal value of CPRSET = 5.11 kΩ. Doubling the
CPRSET value to 10 kΩ doubles the values in Table 2.
A lock is not indicated until there is a programmable number of
consecutive PFD cycles with a time difference less than the lock
detect threshold. The lock detect circuit continues to indicate a
lock until a time difference greater than the unlock threshold
occurs on a single subsequent cycle. For the lock detect to work
properly, the period of the PFD frequency must be greater than
the unlock threshold. The number of consecutive PFD cycles
required for a lock is programmable (0x018[6:5]).
Note that it is possible in certain low (<500 Hz) loop bandwidth,
high phase margin cases that the DLD can chatter during
acquisition, which can cause the AD9516 to automatically enter
and exit holdover. To avoid this problem, it is recommended to
make provisions for a capacitor to ground on the LD pin so that
current source digital lock detect (CSDLD) mode can be used.
REF
X = don’t care.
(MHz)
R
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
P
1
2
1
1
1
2
2
2
2
2
2
2
2
2
2
4
4
A
X
X
X
X
X
X
0
1
2
1
X
0
1
X
0
0
1
1
1
1
1
1
1
1
1
B
1
1
3
4
5
3
3
3
3
4
5
5
5
6
6
3
3
N
1
2
3
4
5
6
6
7
8
9
10
10
11
12
12
12
13
Rev. 0 | Page 31 of 76
f
10
20
30
40
50
60
60
70
80
90
100
100
110
120
120
120
130
VCO
Analog Lock Detect (ALD)
The AD9516 provides an ALD function that can be selected for
use at the LD pin. There are two versions of ALD.
• N-channel open-drain lock detect. This signal requires a pull-
• P-channel open-drain lock detect. This signal requires a pull-
The analog lock detect function requires an RC filter to provide
a logic level indicating lock vs. unlock.
Current Source Digital Lock Detect (CSDLD)
During the PLL locking sequence, it is normal for the DLD
signal to toggle a number of times before remaining steady
when the PLL is completely locked and stable. There may be
applications where it is desirable to have DLD asserted only
after the PLL is solidly locked. This is possible by using the
current source digital lock detect function.
(MHz)
up resistor to the positive supply, VS. The output is normally
high with short, low going pulses. Lock is indicated by the
minimum duty cycle of the low going pulses.
down resistor to GND. The output is normally low with
short, high going pulses. Lock is indicated by the minimum
duty cycle of the high going pulses.
Figure 37. Example of Analog Lock Detect Filter, Using
Mode
FD
FD
FD
FD
FD
FD
DM
DM
DM
DM
FD
DM
DM
FD
DM
DM
DM
ALD
AD9516-5
N-Channel Open-Drain Driver
Notes
P = 1, B = 1 (bypassed)
P = 2, B = 1 (bypassed)
P = 1, B = 3
P = 1, B = 4
P = 1, B = 5
P = 2, B = 3
P = 2 and P + 1 = 3, A = 0, B = 3
P = 2 and P + 1 = 3, A = 1, B = 3
P = 2 and P + 1 = 3, A = 2, B = 3
P = 2 and P + 1 = 3, A = 1, B = 4
P = 2, B = 5
P = 2 and P + 1 = 3, A = 0, B = 5
P = 2 and P + 1 = 3, A = 1, B = 5
P = 2, B = 6
P = 2 and P + 1 = 3, A = 0, B = 6
P = 4 and P + 1 = 5, A = 0, B = 3
P = 4 and P + 1 = 5, A = 1, B = 3
LD
R1
VS = 3.3V
R2
C
V
OUT
AD9516-5