AD9516-5BCPZ-REEL7 Analog Devices Inc, AD9516-5BCPZ-REEL7 Datasheet - Page 35

• Manufacturer Part Number: AD9516-5BCPZ-REEL7
• Description: 10/14 Chan Clock IC W/PLL-no VCO
• Manufacturer: Analog Devices Inc
• Type: Clock Generator, Fanout Distributionr

Specifications of AD9516-5BCPZ-REEL7

• Pll: Yes
• Input: CMOS, LVDS, LVPECL
• Output: CMOS, LVDS, LVPECL
• Number Of Circuits: 1
• Ratio - Input:output: 1:14
• Differential - Input:output: Yes/Yes
• Frequency - Max: 2.4GHz
• Divider/multiplier: Yes/No
• Voltage - Supply: 3.135 V ~ 3.465 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 64-LFCSP
• Frequency-max: 2.4GHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

CLOCK DISTRIBUTION
A clock channel consists of a pair (or double pair, in the case of
CMOS) of outputs that share a common divider. A clock output
consists of the drivers that connect to the output pins. The clock
outputs have either LVPECL or LVDS/CMOS signal levels at
the pins.
The AD9516 has five clock channels: three channels are LVPECL
(six outputs); two channels are LVDS/CMOS (up to four LVDS
outputs, or up to eight CMOS outputs).
Each channel has its own programmable divider that divides
the clock frequency applied to its input. The LVPECL channel
dividers contain a divider that can divide by any integer from
1 to 32. Each LVDS/CMOS channel divider contains two cascaded
dividers that can be set to divide by any integer from 1 to 32.
The total division of the channel is the product of the divide
value of the two cascaded dividers. This allows divide values
of (1 to 32) × (1 to 32), or up to 1024 (notice that this is not all
values from 1 to 1024 but only the set of numbers that are the
product of the two dividers).
The VCO divider can be set to divide by 2, 3, 4, 5, or 6 and must
be used if the external clock signal connected to the CLK input
is greater than 1600 MHz.
The channel dividers allow for a selection of various duty cycles,
depending on the currently set division. That is, for any specific
division, D, the output of the divider can be set to high for N + 1
input clock cycles and low for M + 1 input clock cycles (where
D = N + M + 2). For example, a divide-by-5 can be high for one
divider input cycle and low for four cycles, or a divide-by-5 can
be high for three divider input cycles and low for two cycles.
Other combinations are also possible.
REFIN (REF1)
REFIN (REF2)
CLK
CLK
REF1
REF2
SWITCHOVER
STATUS
REFERENCE
REF_SEL
STATUS
VS
PRESCALER
2, 3, 4, 5, OR 6
1
P, P + 1
DIVIDE BY
GND
0
N DIVIDER
DIVIDER
Figure 41. Reference and CLK Status Monitors
R
COUNTERS
DISTRIBUTION
REFERENCE
A/B
RSET
Rev. 0 | Page 35 of 76
0
1
CLK FREQUENCY
PROGRAMMABLE
PROGRAMMABLE
STATUS
R DELAY
N DELAY
REFMON
The channel dividers include a duty-cycle correction function
that can be disabled. In contrast to the selectable duty cycle
just described, this function can correct a non-50% duty cycle
caused by an odd division. However, this requires that the
division be set by M = N + 1.
In addition, the channel dividers allow a coarse phase offset or
delay to be set. Depending on the division selected, the output
can be delayed by up to 31 input clock cycles. The divider
outputs can also be set to start high or to start low.
Operating Modes
There are two clock distribution operating modes. These operating
modes are shown in Table 25.
It is not necessary to use the VCO divider if the CLK frequency
is less than the maximum channel divider input frequency
(1600 MHz); otherwise, the VCO divider must be used to
reduce the frequency going to the channel dividers.
Table 25. Clock Distribution Operating Modes
Mode
2
1
CLK Direct to LVPECL Outputs
It is possible to connect the CLK directly to the LVPECL outputs,
OUT0 to OUT5. However, the LVPECL outputs may not be able
to provide full a voltage swing at the highest frequencies.
To connect the LVPECL outputs directly to the CLK input, the
VCO divider must be selected as the source to the distribution
section even if no channel uses it.
FREQUENCY
0x1E1[0]
0
1
DETECTOR
DETECT
PHASE
LOCK
CPRSET VCP
CHARGE
PUMP
HOLD
VCO Divider
Used
Not used
AD9516-5
LD
CP
STATUS