AD9516-5BCPZ-REEL7 Analog Devices Inc, AD9516-5BCPZ-REEL7 Datasheet - Page 34

• Manufacturer Part Number: AD9516-5BCPZ-REEL7
• Description: 10/14 Chan Clock IC W/PLL-no VCO
• Manufacturer: Analog Devices Inc
• Type: Clock Generator, Fanout Distributionr

Specifications of AD9516-5BCPZ-REEL7

• Pll: Yes
• Input: CMOS, LVDS, LVPECL
• Output: CMOS, LVDS, LVPECL
• Number Of Circuits: 1
• Ratio - Input:output: 1:14
• Differential - Input:output: Yes/Yes
• Frequency - Max: 2.4GHz
• Divider/multiplier: Yes/No
• Voltage - Supply: 3.135 V ~ 3.465 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 64-LFCSP
• Frequency-max: 2.4GHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

AD9516-5
As in the external holdover mode, the B counter (in the N
divider) is reset synchronously with the charge pump leaving
the high impedance state on the reference path PFD event. This
helps align the edges out of the R and N dividers for faster settling
of the PLL and reduces frequency errors during settling. Because
the prescaler is not reset, this feature works best when the B and R
numbers are close because this results in a smaller phase difference
for the loop to settle out.
After leaving holdover, the loop then reacquires lock and the
LD pin must go high (if 0x01D[3] = 1) before it can reenter
holdover.
The holdover function always responds to the state of the
currently selected reference (0x01C). If the loop loses lock
during a reference switchover (see the Reference Switchover
section), holdover is triggered briefly until the next reference
clock edge at the PFD.
The following registers affect the automatic/internal holdover
function:
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0x018[6:5]—lock detect counter. This changes how many
consecutive PFD cycles with edges inside the lock detect
window are required for the DLD indicator to indicate
lock. This impacts the time required before the LD pin can
begin to charge, as well as the delay from the end of a
holdover event until the holdover function can be reengaged.
0x018[3]—disable digital lock detect. This bit must be set
to a 0 to enable the DLD circuit. Internal/automatic holdover
does not operate correctly without the DLD function enabled.
0x01A[5:0]—lock detect pin control. Set this to 000100b to
put it in the current source lock detect mode if using the
LD pin comparator. Load the LD pin with a capacitor of an
appropriate value.
0x01D[3]—LD pin comparator enable. 1 = enable; 0 =
disable. When disabled, the holdover function always
senses the LD pin as high.
0x01D[1]— external holdover control.
0x01D[0] and 0x01D[2]—holdover enable. If holdover is
disabled, both external and automatic/internal holdover
are disabled.
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In the following example, automatic holdover is configured with:
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The following registers are set (in addition to the normal PLL
registers):
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Frequency Status Monitors
The AD9516 contains three frequency status monitors that are
used to indicate if the PLL reference (or references in the case of
single-ended mode) and the VCO have fallen below a threshold
frequency. Figure 41 is a diagram that shows their location in
the PLL.
The PLL reference monitors have two threshold frequencies:
normal and extended (see Table 13). The reference frequency
monitor thresholds are selected in 0x01F.
Automatic reference switchover, prefer REF1.
Digital lock detect: five PFD cycles, high range window.
Automatic holdover using the LD pin comparator.
0x018[6:5] = 00b; lock detect counter = five cycles.
0x018[4] = 0b; digital lock detect window = high range.
0x018[3] = 0b; disable DLD normal operation.
0x01A[5:0] = 000100b; program LD pin control to current
source lock detect mode.
0x01C[4] = 1b; enable automatic reference switchover.
0x01C[3] = 0b; prefer REF1.
0x01C[2:1] = 11b; enable REF1 and REF2 input buffers.
0x01D[3] = 1b; enable LD pin comparator.
0x01D[2] = 1b; enable the holdover function.
0x01D[1] = 0b; use external holdover mode.
0x01D[0] = 1b; holdover enable.