AD9516-5BCPZ-REEL7 Analog Devices Inc, AD9516-5BCPZ-REEL7 Datasheet - Page 60

• Manufacturer Part Number: AD9516-5BCPZ-REEL7
• Description: 10/14 Chan Clock IC W/PLL-no VCO
• Manufacturer: Analog Devices Inc
• Type: Clock Generator, Fanout Distributionr

Specifications of AD9516-5BCPZ-REEL7

• Pll: Yes
• Input: CMOS, LVDS, LVPECL
• Output: CMOS, LVDS, LVPECL
• Number Of Circuits: 1
• Ratio - Input:output: 1:14
• Differential - Input:output: Yes/Yes
• Frequency - Max: 2.4GHz
• Divider/multiplier: Yes/No
• Voltage - Supply: 3.135 V ~ 3.465 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 64-LFCSP
• Frequency-max: 2.4GHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Reg.
Addr
(Hex) Bit(s) Name
01C
01C
01C
01C
01C
01C
01C
01C
01D
01D
01D
01D
AD9516-5
[7]
[6]
[5]
[4]
[3]
[2]
[1]
[0]
[4]
[3]
[2]
[1]
Select REF2
Stay on REF2 Stay on REF2 after switchover.
REF2
REF1
PLL status
External
Disable
switchover
deglitch
Use REF_SEL
pin
Automatic
reference
switchover
power on
power on
Differential
reference
register
disable
LD pin
comparator
enable
Holdover
enable
holdover
control
Description
[4]
1
1
1
1
1
1
1
Disable or enable the switchover deglitch circuit.
[7] = 0; enable switchover deglitch circuit (default).
[7] = 1; disable switchover deglitch circuit.
If Register 0x01C[5] = 0, select reference for PLL.
[6] = 0; select REF1 (default).
[6] = 1; select REF2.
If Register 0x01C[4] = 0 (manual), set method of PLL reference selection.
[5] = 0; use Register 0x01C[6] (default).
[5] = 1; use REF_SEL pin.
Automatic or manual reference switchover. Single-ended reference mode must be selected by
Register 0x01C[0] = 0.
[4] = 0; manual reference switchover (default).
[4] = 1; automatic reference switchover.
[3] = 0; return to REF1 automatically when REF1 status is good again (default).
[3] = 1; stay on REF2 after switchover. Do not automatically return to REF1.
When automatic reference switchover is disabled, this bit turns the REF2 power on.
[2] = 0; REF2 power off (default).
[2] = 1; REF2 power on.
When automatic reference switchover is disabled, this bit turns the REF1 power on.
[1] = 0; REF1 power off (default).
[1] = 1; REF1 power on.
Selects the PLL reference mode, differential or single-ended. Single-ended must be selected for the
automatic switchover or REF1 and REF2 to work.
[0] = 0; single-ended reference mode (default).
[0] = 1; differential reference mode.
Disables the PLL status register readback.
[4] = 0; PLL status register enable (default).
[4] = 1; PLL status register disable.
Enables the LD pin voltage comparator. This is used with the LD pin current source lock detect mode.
When in the internal (automatic) holdover mode, this enables the use of the voltage on the LD pin to
determine if the PLL was previously in a locked state (see Figure 40). Otherwise, this can be used with
the REFMON and STATUS pins to monitor the voltage on the LD pin.
[3] = 0; disable LD pin comparator; internal/automatic holdover controller treats this pin as true/high (default).
[3] = 1; enable LD pin comparator.
Along with 0x01D[0] enables the holdover function.
[2] = 0; holdover disabled (default).
[2] = 1; holdover enabled.
Enables the external hold control through the SYNC pin. (This disables the internal holdover mode.)
[1] = 0; automatic holdover mode—holdover controlled by automatic holdover circuit (default).
[1] = 1; external holdover mode—holdover controlled by SYNC pin.
[3]
1
1
1
1
1
1
1
[2]
0
0
0
1
1
1
1
[1]
0
1
1
0
0
1
1
[0]
1
0
1
0
1
0
1
Level or
Dynamic
Signal
LVL
LVL
LVL
LVL
LVL
LVL
LVL
Rev. 0 | Page 60 of 76
Signal at REFMON Pin
(Status of REF1 frequency) AND (Status of REF2 frequency).
(DLD) AND (Status of selected reference) AND (Status of CLK) .
Status of CLK frequency (active low).
Selected reference (low = REF2, high = REF1).
Digital lock detect (DLD); active low.
Holdover active (active low).
LD pin comparator output (active low).