AD9516-5BCPZ-REEL7 Analog Devices Inc, AD9516-5BCPZ-REEL7 Datasheet - Page 39

• Manufacturer Part Number: AD9516-5BCPZ-REEL7
• Description: 10/14 Chan Clock IC W/PLL-no VCO
• Manufacturer: Analog Devices Inc
• Type: Clock Generator, Fanout Distributionr

Specifications of AD9516-5BCPZ-REEL7

• Pll: Yes
• Input: CMOS, LVDS, LVPECL
• Output: CMOS, LVDS, LVPECL
• Number Of Circuits: 1
• Ratio - Input:output: 1:14
• Differential - Input:output: Yes/Yes
• Frequency - Max: 2.4GHz
• Divider/multiplier: Yes/No
• Voltage - Supply: 3.135 V ~ 3.465 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 64-LFCSP
• Frequency-max: 2.4GHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

The possibilities for the duty cycle of the output clock from
Divider 3 and Divider 4 are shown in Table 35 through Table 39.
Table 35. Divider 3 and Divider 4 Duty Cycle; VCO Divider
Used; Duty Cycle Correction Off (DCCOFF = 1)
VCO
Divider
Even
Odd = 3
Odd = 5
Even
Odd
Even
Odd
Table 36. Divider 3 and Divider 4 Duty Cycle; VCO Divider
Not Used; Duty Cycle Correction Off (DCCOFF = 1)
Input Clock
Duty Cycle
50%
X%
50%
X%
50%
X%
Table 37. Divider 3 and Divider 4 Duty Cycle; VCO Divider
Used; Duty Cycle Correction On (DCCOFF = 0); VCO Divider
Input Duty Cycle = 50%
VCO
Divider
Even
Odd
Even
Odd
Even
Odd
Even
Odd
Even
Odd
Even
Odd
N
Bypassed
Bypassed
Even (N
Even (N
Odd (M
Odd (M
Even (N
Even (N
Odd (M
Odd (M
Odd (M
Odd (M
N
Bypassed
Bypassed
Bypassed
Even, Odd
Even, Odd
Even, Odd
Even, Odd
X.1
X.1
+ M
+ M
N
Bypassed
Bypassed
Even, Odd
Even, Odd
Even, Odd
Even, Odd
D
X.1
X.1
X.1
X.1
X.1
X.1
X.1
X.1
D
X.1
X.1
X.1
X.1
X.1
X.1
+ M
X.1
= N
= N
= N
= N
= N
= N
D
= M
= M
= M
= M
+ 2
+ 2
X.1
X.1
X.1
X.1
X.1
X.1
X.1
X.1
X.1
X.1
X.1
X.1
+ 1)
+ 1)
+ 1)
+ 1)
+ 1)
+ 1)
+ 2
)
)
)
)
Bypassed
Even, Odd
N
Bypassed
Bypassed
Bypassed
Bypassed
Even, Odd
X.2
+ M
N
Bypassed
Bypassed
Bypassed
Bypassed
Even, Odd
Even, Odd
N
Bypassed
Bypassed
Bypassed
Bypassed
Bypassed
Bypassed
Even (N
Even (N
Even (N
Even (N
Odd (M
Odd (M
D
X.2
X.2
X.2
X.2
+ M
+ M
D
+ 2
X.2
X.2
X.2
D
X.2
X.2
X.2
X.2
X.2
X.2
X.2
= N
= N
+ 2
= M
= M
= M
= M
+ 2
50%
33.3%
40%
(N
(N
(N
(N
(N
(N
(N
(N
X.2
X.2
Output Duty Cycle
X.2
X.2
X.2
X.2
+ 1)
+ 1)
X.1
X.1
X.1
X.1
X.2
X.2
X.2
X.2
)
)
)
)
Output
Duty Cycle
50%
X%
(N
(N
(N
(N
(N
(N
(N
(N
+ 1)/
+ M
+ 1)/
+ M
+ 1)/
+ M
+ 1)/
+ M
X.1
X.1
X.1
X.1
X.2
X.2
X.2
X.2
X.1
X.1
X.2
X.2
+ 1)/
+ M
+ 1)/
+ M
+ 1)/
+ M
+ 1)/
+ M
Output
Duty
Cycle
50%
50%
50%
50%
50%
50%
50%
50%
50%
50%
50%
50%
+ 2)
+ 2)
+ 2)
+ 2)
X.1
X.1
X.2
X.2
+ 2)
+ 2)
+ 2)
+ 2)
Rev. 0 | Page 39 of 76
Table 38. Divider 3 and Divider 4 Duty Cycle; VCO Divider
Used; Duty Cycle Correction On (DCCOFF = 0); VCO
Divider Input Duty Cycle = X%
VCO
Divider
Even
Odd = 3
Odd = 5
Even
Odd
Even
Odd = 3
Odd = 5
Even
Odd
Even
Odd
Even
Odd = 3
Odd = 5
N
Bypassed
Bypassed
Bypassed
Even
(N
Even
(N
Odd
(M
Odd
(M
Odd
(M
Even
(N
Even
(N
Odd
(M
Odd
(M
Odd
(M
Odd
(M
Odd
(M
X.1
X.1
X.1
X.1
X.1
X.1
X.1
X.1
X.1
X.1
X.1
X.1
X.1
+ M
= M
= M
= N
= N
= N
= M
= M
= N
= N
= N
= N
= N
D
X.1
X.1
X.1
X.1
X.1
X.1
X.1
X.1
X.1
X.1
X.1
X.1
X.1
X.1
+ 1)
+ 1)
+ 1)
+ 1)
+ 1)
+ 1)
+ 1)
+ 1)
)
)
)
)
+ 2
N
Bypassed
Bypassed
Bypassed
Bypassed
Bypassed
Bypassed
Bypassed
Bypassed
Even
(N
Even
(N
Even
(N
Even
(N
Odd
(M
Odd
(M
Odd
(M
X.2
X.2
X.2
X.2
X.2
X.2
X.2
X.2
+ M
= M
= M
= M
= M
= N
= N
= N
D
X.2
X.2
X.2
X.2
X.2
X.2
X.2
X.2
X.2
+ 1)
+ 1)
+ 1)
)
)
)
)
+ 2
Output
Duty Cycle
50%
(1 + X%)/3
(2 + X%)/5
50%
50%
50%
(3N
(6N
(5N
(10N
50%
50%
50%
50%
50%
(6N
9N
(3(2N
(2N
(10N
15N
(5(2 N
(2 N
X.2
X.1
X.1
X.1
X.1
X.2
AD9516-5
X.2
X.2
X.1
X.1
+ 13 + X%)/
N
X.1
+ 4 + X%)/
+ 9)
+ 7 + X%)/
+ 3))
X.1
N
+ 22 + X%)/
+ 3))
X.2
+ 15)
X.2
+ 3)
+ 3)
+ 9N
+ 15N
X.1
X.1
+
+