AD9516-5BCPZ-REEL7 Analog Devices Inc, AD9516-5BCPZ-REEL7 Datasheet - Page 73

• Manufacturer Part Number: AD9516-5BCPZ-REEL7
• Description: 10/14 Chan Clock IC W/PLL-no VCO
• Manufacturer: Analog Devices Inc
• Type: Clock Generator, Fanout Distributionr

Specifications of AD9516-5BCPZ-REEL7

• Pll: Yes
• Input: CMOS, LVDS, LVPECL
• Output: CMOS, LVDS, LVPECL
• Number Of Circuits: 1
• Ratio - Input:output: 1:14
• Differential - Input:output: Yes/Yes
• Frequency - Max: 2.4GHz
• Divider/multiplier: Yes/No
• Voltage - Supply: 3.135 V ~ 3.465 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 64-LFCSP
• Frequency-max: 2.4GHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Thevenin-equivalent termination uses a resistor network to
provide 50 Ω termination to a dc voltage that is below V
the LVPECL driver. In this case, VS_LVPECL on the AD9520
should equal V
combination shown results in a dc bias point of VS_LVPECL − 2 V,
the actual common-mode voltage is VS_LVPECL − 1.3 V because
there is additional current flowing from the AD9520 LVPECL
driver through the pull-down resistor.
The circuit is identical for the case where VS_LVPECL = 2.5 V,
except that the pull-down resistor is 62.5 Ω and the pull-up is 250 Ω.
LVDS CLOCK DISTRIBUTION
The AD9516 provides four clock outputs (OUT6 to OUT9) that
are selectable as either CMOS or LVDS level outputs. LVDS is a
differential output option that uses a current mode output stage.
The nominal current is 3.5 mA, which yields 350 mV of output
swing across a 100 Ω resistor. The LVDS output meets or exceeds
all ANSI/TIA/EIA-644 specifications.
A recommended termination circuit for the LVDS outputs is
shown in Figure 61.
See the AN-586 Application Note at
information on LVDS.
CMOS CLOCK DISTRIBUTION
The AD9516 provides four clock outputs (OUT6 to OUT9)
that are selectable as either CMOS or LVDS level outputs.
When selected as CMOS, each output becomes a pair of CMOS
outputs, each of which can be individually turned on or off and
set as noninverting or inverting. These outputs are 3.3 V CMOS
compatible.
VS
LVDS
S
of the receiving buffer. Although the resistor
Figure 61. LVDS Output Termination
DIFFERENTIAL (COUPLED)
100Ω
www.analog.com
100Ω
LVDS
VS
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Whenever single-ended CMOS clocking is used, some general
guidelines should be followed.
Point-to-point nets should be designed such that a driver has
only one receiver on the net, if possible. This allows for simple
termination schemes and minimizes ringing due to possible
mismatched impedances on the net. Series termination at the
source is generally required to provide transmission line matching
and/or to reduce current transients at the driver. The value of
the resistor is dependent on the board design and timing
requirements (typically 10 Ω to 100 Ω is used). CMOS outputs
are also limited in terms of the capacitive load or trace length
that they can drive. Typically, trace lengths less than 3 inches
are recommended to preserve signal rise/fall times and preserve
signal integrity.
Termination at the far end of the PCB trace is a second option.
The CMOS outputs of the AD9516 do not supply enough current
to provide a full voltage swing with a low impedance resistive, far-
end termination, as shown in Figure 63. The far-end termination
network should match the PCB trace impedance and provide the
desired switching point. The reduced signal swing may still meet
receiver input requirements in some applications. This can be
useful when driving long trace lengths on less critical nets.
Because of the limitations of single-ended CMOS clocking,
consider using differential outputs when driving high speed
signals over long traces. The AD9516 offers both LVPECL and
LVDS outputs that are better suited for driving long traces where
the inherent noise immunity of differential signaling provides
superior performance for clocking converters.
Figure 63. CMOS Output with Far-End Termination
CMOS
Figure 62. Series Termination of CMOS Output
CMOS
10Ω
10Ω
MICROSTRIP
50Ω
(1.0 INCH)
60.4Ω
VS
100Ω
100Ω
CMOS
CMOS
AD9516-5