AD9516-5BCPZ-REEL7 Analog Devices Inc, AD9516-5BCPZ-REEL7 Datasheet - Page 70

• Manufacturer Part Number: AD9516-5BCPZ-REEL7
• Description: 10/14 Chan Clock IC W/PLL-no VCO
• Manufacturer: Analog Devices Inc
• Type: Clock Generator, Fanout Distributionr

Specifications of AD9516-5BCPZ-REEL7

• Pll: Yes
• Input: CMOS, LVDS, LVPECL
• Output: CMOS, LVDS, LVPECL
• Number Of Circuits: 1
• Ratio - Input:output: 1:14
• Differential - Input:output: Yes/Yes
• Frequency - Max: 2.4GHz
• Divider/multiplier: Yes/No
• Voltage - Supply: 3.135 V ~ 3.465 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 64-LFCSP
• Frequency-max: 2.4GHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Reg.
Addr
(Hex) Bit(s)
19B
19B
19C
19C
19C
19C
19C
19C
19D
19E
19E
19F
19F
1A0
1A0
1A1
1A1
1A1
1A1
1A1
AD9516-5
[7:4]
[3:0]
[5]
[4]
[3]
[2]
[1]
[0]
[0]
[7:4]
[3:0]
[7:4]
[3:0]
[7:4]
[3:0]
[5]
[4]
[3]
[2]
[1]
Name
Low Cycles Divider 3.2
High Cycles Divider 3.2
Bypass Divider 3.2
Bypass Divider 3.1
Divider 3 nosync
Divider 3 force high
Start High Divider 3.2
Start High Divider 3.1
Divider 3 DCCOFF
Low Cycles Divider 4.1
High Cycles Divider 4.1
Phase Offset Divider 4.2
Phase Offset Divider 4.1
Low Cycles Divider 4.2
High Cycles Divider 4.2
Bypass Divider 4.2
Bypass Divider 4.1
Divider 4 nosync
Divider 4 force high
Start High Divider 4.2
Description
Number of clock cycles (minus 1) of the Divider 3.2 input during which the Divider 3.2 output
stays low. A value of 0x7 means the divider is low for eight input clock cycles (default: 0x1).
Number of clock cycles (minus 1) of the Divider 3.2 input during which the Divider 3.2 output
stays high. A value of 0x7 means the divider is low for eight input clock cycles (default: 0x1).
Bypass (and power-down) 3.2 divider logic, route clock to 3.2 output.
[5] = 0; do not bypass (default).
[5] = 1; bypass.
Bypass (and power-down) 3.1 divider logic, route clock to 3.1 output.
[4] = 0; do not bypass (default).
[4] = 1; bypass.
Nosync.
[3] = 0; obey chip-level SYNC signal (default).
[3] = 1; ignore chip-level SYNC signal.
Force Divider 3 output high. Requires that nosync also be set.
[2] = 0; force low (default).
[2] = 1; force high.
Divider 3.2 start high/low.
[1] = 0; start low (default).
[1] = 1; start high.
Divider 3.1 start high/low.
[0] = 0; start low (default).
[0] = 1; start high.
Duty-cycle correction function.
[0] = 0; enable duty-cycle correction (default).
[0] = 1; disable duty-cycle correction.
Number of clock cycles (minus 1) of the Divider 4.1 input during which the Divider 4.1 output
stays low. A value of 0x7 means the divider is low for eight input clock cycles (default: 0x2).
Number of clock cycles (minus 1) of the Divider 4.1 input during which the Divider 4.1 output
stays high. A value of 0x7 means the divider is low for eight input clock cycles (default: 0x2).
Refer to LVDSCMOS channel divider function description (default: 0x0).
Refer to LVDSCMOS channel divider function description (default: 0x0).
Number of clock cycles (minus 1) of the Divider 4.2 input during which the Divider 4.2 output
stays low. A value of 0x7 means the divider is low for eight input clock cycles (default: 0x1).
Number of clock cycles (minus 1) of the Divider 4.2 input during which the Divider 4.2 output
stays high. A value of 0x7 means the divider is low for eight input clock cycles (default: 0x1).
Bypass (and power down) 4.2 divider logic, route clock to 4.2 output.
[5] = 0; do not bypass (default).
[5] = 1; bypass.
Bypass (and power down) 4.1 divider logic, route clock to 4.1 output.
[4] = 0; do not bypass (default).
[4] = 1; bypass.
Nosync.
[3] = 0; obey chip-level SYNC signal (default).
[3] = 1; ignore chip-level SYNC signal.
Force Divider 4 output high. Requires that nosync also be set.
[2] = 0; force low (default).
[2] = 1; force high.
Divider 4.2 start high/low.
[1] = 0; start low (default).
[1] = 1; start high.
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