AD9516-5BCPZ-REEL7 Analog Devices Inc, AD9516-5BCPZ-REEL7 Datasheet - Page 42

• Manufacturer Part Number: AD9516-5BCPZ-REEL7
• Description: 10/14 Chan Clock IC W/PLL-no VCO
• Manufacturer: Analog Devices Inc
• Type: Clock Generator, Fanout Distributionr

Specifications of AD9516-5BCPZ-REEL7

• Pll: Yes
• Input: CMOS, LVDS, LVPECL
• Output: CMOS, LVDS, LVPECL
• Number Of Circuits: 1
• Ratio - Input:output: 1:14
• Differential - Input:output: Yes/Yes
• Frequency - Max: 2.4GHz
• Divider/multiplier: Yes/No
• Voltage - Supply: 3.135 V ~ 3.465 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 64-LFCSP
• Frequency-max: 2.4GHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

AD9516-5
INPUT TO CHANNEL DIVIDER
A SYNC operation brings all outputs that have not been excluded
(by the nosync bit) to a preset condition before allowing the
outputs to begin clocking in synchronicity. The preset condition
takes into account the settings in each of the channel’s start high bit
and its phase offset. These settings govern both the static state of
each output when the SYNC operation is happening and the state
and relative phase of the outputs when they begin clocking again
upon completion of the SYNC operation. Between outputs and
after synchronization, this allows for the setting of phase offsets.
The AD9516 outputs are in pairs, sharing a channel divider per
pair (two pairs of pairs, four outputs, in the case of CMOS). The
synchronization conditions apply to both outputs of a pair.
Each channel (a divider and its outputs) can be excluded from
any SYNC operation by setting the nosync bit of the channel.
Channels that are set to ignore SYNC (excluded channels) do
not set their outputs static during a SYNC operation, and their
outputs are not synchronized with those of the nonexcluded
channels.
SYNC PIN
SYNC PIN
INPUT TO CHANNEL DIVIDER
CHANNEL DIVIDER
INPUT TO VCO DIVIDER
OUTPUT CLOCKING
CHANNEL DIVIDER
INPUT TO CLK
CHANNEL DIVIDER
OUTPUT CLOCKING
OUTPUT OF
CHANNEL DIVIDER
OUTPUT OF
Figure 44. SYNC Timing when VCO Divider Is Used—CLK or VCO Is Input
Figure 45. SYNC Timing when VCO Divider Is Not Used—CLK Input Only
1
14 TO 15 CYCLES AT CHANNEL DIVIDER INPUT + 1 CYCLE AT CLK INPUT
1
14 TO 15 CYCLES AT CHANNEL DIVIDER INPUT + 1 CYCLE AT VCO DIVIDER INPUT
2
2
3
CHANNEL DIVIDER OUTPUT STATIC
3
CHANNEL DIVIDER OUTPUT STATIC
4
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5
5
6
6
Clock Outputs
The AD9516 offers three output level choices: LVPECL, LVDS,
and CMOS. OUT0 to OUT5 are LVPECL differential outputs;
and OUT6 to OUT9 are LVDS/CMOS outputs. These outputs
can be configured as either LVDS differential or as pairs of
single-ended CMOS outputs.
LVPECL Outputs: OUT0 to OUT5
The LVPECL differential voltage (V
to 960 mV, see 0x0F0:5[3:2]. The LVPECL outputs have dedicated
pins for power supply (VS_LVPECL), allowing a separate power
supply to be used. VS_LVPECL can be from 2.5 V to 3.3 V.
The LVPECL output polarity can be set as noninverting or
inverting, which allows for the adjustment of the relative
polarity of outputs within an application without requiring a
board layout change. Each LVPECL output can be powered
down or powered up as needed. Because of the architecture of
the LVPECL output stages, there is the possibility of electrical
overstress and breakdown under certain power-down conditions.
7
7
8
8
9
9
10
10
11
11
12
12
13
14
13
OD
) is selectable (from 400 mV
1
14
1
OUTPUT CLOCKING
CHANNEL DIVIDER
OUTPUT CLOCKING
CHANNEL DIVIDER