AD9522-0BCPZ Analog Devices Inc, AD9522-0BCPZ Datasheet - Page 15

• Manufacturer Part Number: AD9522-0BCPZ
• Description: 12- Channel Clock Generator With Integra
• Manufacturer: Analog Devices Inc
• Type: Clock Generator, Fanout Distributionr

Specifications of AD9522-0BCPZ

• Pll: Yes
• Input: CMOS, LVDS, LVPECL
• Output: CMOS, LVDS
• Number Of Circuits: 1
• Ratio - Input:output: 2:12, 2:24
• Differential - Input:output: Yes/Yes
• Frequency - Max: 2.95GHz
• Divider/multiplier: Yes/No
• Voltage - Supply: 3.135 V ~ 3.465 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 64-LFCSP
• Frequency-max: 2.8GHz
• Operating Temperature (min): -40C
• Operating Temperature Classification: Industrial
• Operating Temperature (max): 85C
• Rad Hardened: No
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

POWER DISSIPATION
Table 18.
Parameter
POWER DISSIPATION, CHIP
POWER DELTAS, INDIVIDUAL FUNCTIONS
Power-On Default
PLL Locked; One LVDS Output Enabled
PLL Locked; One CMOS Output Enabled
Distribution Only Mode; VCO Divider On;
Distribution Only Mode; VCO Divider Off;
Maximum Power, Full Operation
PD Power-Down
PD Power-Down, Maximum Sleep
VCP Supply
VCO Divider On/Off
REFIN (Differential) Off
REF1, REF2 (Single-Ended) On/Off
VCO On/Off
PLL Dividers and Phase Detector On/Off
LVDS Channel
LVDS Driver
CMOS Channel
CMOS Driver On/Off
Channel Divider Enabled
Zero Delay Block On/Off
One LVDS Output Enabled
One LVDS Output Enabled
Min
Typ
0.88
0.54
0.55
0.36
0.33
1.1
35
27
8
33
25
16
60
54
118
11
120
16
33
30
Max
1.0
0.63
0.66
0.43
0.4
1.3
50
43
2.3
43
31
22
95
67
146
15
154
30
40
35
Rev. 0 | Page 15 of 84
Unit
W
W
W
W
W
W
mW
mW
mW
mW
mW
mW
mW
mW
mW
mW
mW
mW
mW
mW
Test Conditions/Comments
Does not include power dissipated in external resistors; all LVDS
outputs terminated with 100 Ω across differential pair; all CMOS
outputs have 10 pF capacitive loading
No clock; no programming; default register values
f
one LVDS output and output divider enabled; zero delay off;
I
f
one CMOS output and output divider enabled; zero delay off;
I
f
and output divider enabled; zero delay off
f
output and output divider enabled; zero delay off
PLL on; internal VCO = 2750 MHz; VCO divider = 2; all channel
dividers on; 12 LVDS outputs @ 125 MHz; zero delay on
PD pin pulled low; does not include power dissipated in
termination resistors
PD pin pulled low; PLL power-down, 0x010[1:0] = 01b; power-
down SYNC, 0x230[2] = 1b; power-down distribution reference,
0x230[1] = 1b
PLL operating; typical closed-loop configuration
Power delta when a function is enabled/disabled
VCO divider not used
Delta between reference input off and differential reference
input mode
Delta between reference inputs off and one singled-ended
reference enabled; double this number if both REF1 and REF2
are powered up
Internal VCO disabled; CLK input selected
PLL off to PLL on, normal operation; no reference enabled
No LVDS output on to one LVDS output on; channel divider set to 1
Second LVDS output turned on, same channel
No CMOS output on to one CMOS output on; channel divider
set to 1; f
Additional CMOS outputs within the same channel turned on
Delta between divider bypassed (divide-by-1) and divide-by-2 to
divide-by-32
CP
CP
REF
REF
CLK
CLK
= 4.8 mA
= 4.8 mA
= 25 MHz; f
= 25 MHz; f
= 2.4 GHz; f
= 2.4 GHz; f
OUT
= 62.5 MHz and 10 pF of capacitive loading
OUT
OUT
OUT
OUT
= 250 MHz; VCO = 2750 MHz; VCO divider = 2;
= 62.5 MHz; VCO = 2750 MHz; VCO divider = 2;
= 200 MHz; VCO divider = 2; one LVDS output
= 200 MHz; VCO divider bypassed; one LVDS
AD9522-0