AD9522-0BCPZ Analog Devices Inc, AD9522-0BCPZ Datasheet - Page 63

• Manufacturer Part Number: AD9522-0BCPZ
• Description: 12- Channel Clock Generator With Integra
• Manufacturer: Analog Devices Inc
• Type: Clock Generator, Fanout Distributionr

Specifications of AD9522-0BCPZ

• Pll: Yes
• Input: CMOS, LVDS, LVPECL
• Output: CMOS, LVDS
• Number Of Circuits: 1
• Ratio - Input:output: 2:12, 2:24
• Differential - Input:output: Yes/Yes
• Frequency - Max: 2.95GHz
• Divider/multiplier: Yes/No
• Voltage - Supply: 3.135 V ~ 3.465 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 64-LFCSP
• Frequency-max: 2.8GHz
• Operating Temperature (min): -40C
• Operating Temperature Classification: Industrial
• Operating Temperature (max): 85C
• Rad Hardened: No
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Addr
(Hex)
193
194
195
196
197
198
199
19A
19B
19C
to
1DF
VCO Divider and CLK Input
1E0
1E1
1E2
to
22A
System
230
231
Update All Registers
232
233
to
9FF
EEPROM Buffer Segment
A00
A01
A02
A03
A04
Parameter
Divider 1 (PECL)
Divider 2 (PECL)
Divider 3 (PECL)
VCO divider
Input CLKs
Power-down
and SYNC
IO_UPDATE
EEPROM
Buffer Segment
Register 1
EEPROM
Buffer Segment
Register 2
EEPROM
Buffer Segment
Register 3
EEPROM
Buffer Segment
Register 4
EEPROM
Buffer Segment
Register 5
Bit 7 (MSB)
Divider 1
bypass
Divider 2
bypass
Divider 3
bypass
0
0
EEPROM Buffer Segment Register 2 (default: Bits[15:8] of starting register address for Group 1)
EEPROM Buffer Segment Register 5 (default: Bits[15:8] of starting register address for Group 2)
EEPROM Buffer Segment Register 3 (default: Bits[7:0] of starting register address for Group 1)
Unused
Divider 1 low cycles
Divider 2 low cycles
Divider 3 low cycles
Bit 6
Divider 1
ignore
SYNC
Divider 2
ignore
SYNC
Divider 3
ignore
SYNC
Unused
Unused
Unused
Unused
Unused
Unused
EEPROM Buffer Segment Register 1 (default: number of bytes for Group 1)
EEPROM Buffer Segment Register 4 (default: number of bytes for Group 2)
Bit 5
Divider 1
force
high
Divider 2
force
high
Divider 3
force
high
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Bit 4
Divider 1
start high
Divider 2
start high
Divider 3
start high
Power -
down
clock
input
section
Unused
Unused
Unused
Unused
Bit 3
Unused
Unused
Power-
down VCO
clock
interface
Disable
power-on
SYNC
Unused
Unused
Bit 2
Channel 3
power-
down
Power-
down
VCO
and CLK
Power-
down
SYNC
Channel 1
Channel 2
power-
power-
down
down
Divider 1 high cycles
Divider 2 high cycles
Divider 3 high cycles
phase offset
phase offset
phase offset
Divider 1
Divider 2
Divider 3
Unused
Bit 1
Select
VCO or CLK
Power-
down
distribution
reference
Reserved
Reserved
Reserved
VCO divider
Bit 0 (LSB)
Disable
Divider 3
DCC
Bypass VCO
divider
Soft
SYNC
IO_UPDATE
(self-clearing)
Divider 1
Divider 2
Disable
Disable
DCC
DCC
AD9522-0
Default
Value
(Hex)
33
00
00
11
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
02
00
00