AD9522-0BCPZ Analog Devices Inc, AD9522-0BCPZ Datasheet - Page 36

• Manufacturer Part Number: AD9522-0BCPZ
• Description: 12- Channel Clock Generator With Integra
• Manufacturer: Analog Devices Inc
• Type: Clock Generator, Fanout Distributionr

Specifications of AD9522-0BCPZ

• Pll: Yes
• Input: CMOS, LVDS, LVPECL
• Output: CMOS, LVDS
• Number Of Circuits: 1
• Ratio - Input:output: 2:12, 2:24
• Differential - Input:output: Yes/Yes
• Frequency - Max: 2.95GHz
• Divider/multiplier: Yes/No
• Voltage - Supply: 3.135 V ~ 3.465 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 64-LFCSP
• Frequency-max: 2.8GHz
• Operating Temperature (min): -40C
• Operating Temperature Classification: Industrial
• Operating Temperature (max): 85C
• Rad Hardened: No
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

AD9522-0
Prescaler
The prescaler of the AD9522 allows for two modes of operation:
a fixed divide (FD) mode of 1, 2, or 3, and a dual modulus
(DM) mode where the prescaler divides by P and (P + 1) {2 and
3, 4 and 5, 8 and 9, 16 and 17, or 32 and 33}. The prescaler
modes of operation are given in Table 52, 0x016[2:0]. Not all
modes are available at all frequencies (see Table 2).
When operating the AD9522 in dual modulus mode, P/(P + 1),
the equation used to relate the input reference frequency to the
VCO output frequency is
However, when operating the prescaler in FD Mode 1,
FD Mode 2, or FD Mode 3, the A counter is not used (A = 0)
and the equation simplifies to
When A = 0, the divide is a fixed divide of P = 2, 4, 8, 16, or 32.
By using combinations of DM and FD modes, the AD9522 can
achieve values of N all the way down to N = 1. Table 29 shows
how a 10 MHz reference input can be locked to any integer
multiple of N.
Note that the same value of N can be derived in different ways,
as illustrated by the case of N = 12. The user can choose a fixed
divide mode P = 2 with B = 6, use the dual modulus mode 2/3
with A = 0, B = 6, or use the dual modulus mode 4/5 with
A = 0, B = 3.
Table 29. How a 10 MHz Reference Input Can Be Locked to Any Integer Multiple of N
f
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
1
REF
X = don’t care.
(MHz)
f
f
VCO
VCO
= (f
= (f
REF
REF
R
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
/R) × (P × B + A) = f
/R) × (P × B) = f
P
1
2
1
1
1
2
2
2
2
2
2
2
2
2
2
4
4
A
X
X
X
X
X
X
0
1
2
1
X
0
1
X
0
0
1
1
1
1
1
1
1
1
1
REF
× N/R
B
1
1
3
4
5
3
3
3
3
4
5
5
5
6
6
3
3
REF
× N/R
N
1
2
3
4
5
6
6
7
8
9
10
10
11
12
12
12
13
f
10
20
30
40
50
60
60
70
80
90
100
100
110
120
120
120
130
VCO
(MHz)
Rev. 0 | Page 36 of 84
Mode
DM
DM
DM
DM
FD
DM
DM
FD
DM
DM
DM
FD
FD
FD
FD
FD
FD
A and B Counters
The B counter must be ≥3 or bypassed, and unlike the R
counter, A = 0 is actually zero.
The maximum input frequency to the A/B counter is reflected
in the maximum prescaler output frequency (~300 MHz) specified
in Table 2. This is the prescaler input frequency (VCO or CLK)
divided by P. For example, dual modulus P = 8/9 mode is not
allowed if the VCO frequency is greater than 2400 MHz
because the frequency going to the A/B counter is too high.
When the AD9522 B counter is bypassed (B = 1), the A counter
should be set to zero, and the overall resulting divide is equal to
the prescaler setting, P. The possible divide ratios in this mode
are 1, 2, 3, 4, 8, 16, and 32. This mode is only useful when an
external VCO/VCXO is used because the frequency range of the
internal VCO requires an overall feedback divider greater than 32.
Although manual reset is not normally required, the A/B counters
have their own reset bit. Alternatively, the A and B counters can be
reset using the shared reset bit of the R, A, and B counters. Note
that these reset bits are not self-clearing.
R, A, and B Counters: SYNC Pin Reset
The R, A, and B counters can be reset simultaneously through the
SYNC pin. This function is controlled by 0x019[7:6] (see
The
R and N Divider Delays
Both the R and N dividers feature a programmable delay cell.
These delays can be enabled to allow adjustment of the phase
relationship between the PLL reference clock and the VCO or
CLK. Each delay is controlled by three bits. The total delay
range is about 1 ns. See 0x019 in Table 2 and Table 52.
SYNC pin reset is disabled by default.
Notes
P = 1, B = 1 (bypassed)
P = 2, B = 1 (bypassed)
P = 1, B = 3
P = 1, B = 4
P = 1, B = 5
P = 2, B = 3
P and P + 1 = 2 and 3, A = 0, B = 3
P and P + 1 = 2 and 3, A = 1, B = 3
P and P + 1 = 2 and 3, A = 2, B = 3
P and P + 1 = 2 and 3, A = 1, B = 4
P = 2, B = 5
P and P + 1 = 2 and 3, A = 0, B = 5
P and P + 1 = 2 and 3, A = 1, B = 5
P = 2, B = 6
P and P + 1 = 2 and 3, A = 0, B = 6
P and P + 1 = 4 and 5, A = 0, B = 3
P and P + 1 = 4 and 5, A = 1, B = 3
Table 52
).