AD9522-0BCPZ Analog Devices Inc, AD9522-0BCPZ Datasheet - Page 61
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AD9522-0BCPZ
Manufacturer Part Number
AD9522-0BCPZ
Description
12- Channel Clock Generator With Integra
Manufacturer
Analog Devices Inc
Type
Clock Generator, Fanout Distributionr
Datasheet
1.AD9522-0BCPZ-REEL7.pdf
(84 pages)
Specifications of AD9522-0BCPZ
Pll
Yes
Input
CMOS, LVDS, LVPECL
Output
CMOS, LVDS
Number Of Circuits
1
Ratio - Input:output
2:12, 2:24
Differential - Input:output
Yes/Yes
Frequency - Max
2.95GHz
Divider/multiplier
Yes/No
Voltage - Supply
3.135 V ~ 3.465 V
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
64-LFCSP
Frequency-max
2.8GHz
Operating Temperature (min)
-40C
Operating Temperature Classification
Industrial
Operating Temperature (max)
85C
Rad Hardened
No
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
AD9522-0BCPZ
Manufacturer:
Analog Devices Inc
Quantity:
135
Company:
Part Number:
AD9522-0BCPZ
Manufacturer:
AD
Quantity:
25
Part Number:
AD9522-0BCPZ
Manufacturer:
ADI/亚德诺
Quantity:
20 000
REGISTER MAP
Register addresses that are not listed in Table 48 are not used, and writing to those registers has no effect. Writing to register addresses
marked unused should have 00h written to them, unless otherwise noted.
Table 48. Register Map Overview
Addr
(Hex)
Serial Port Configuration
000
001
002
003
004
EEPROM ID
005
006
007
to
00F
PLL
010
011
012
013
014
015
016
017
018
019
01A
01B
01C
01D
Parameter
Serial port config
(SPI mode)
Serial port config
(I²C mode)
Readback
control
EEPROM
customer
version ID
PFD charge
R counter
A counter
B counter
PLL_CTRL_1
PLL_CTRL_2
PLL_CTRL_3
PLL_CTRL_4
PLL_CTRL_5
PLL_CTRL_6
PLL_CTRL_7
PLL_CTRL_8
pump
Bit 7 (MSB)
SDO active
Set CP pin
to VCP/2
Enable CMOS
reference input
dc offset
Enable STATUS
pin divider
Enable VCO
frequency
monitor
Disable
switchover
deglitch
Enable
STATUS_EEPROM
at STATUS pin
PFD polarity
R, A, B counters
SYNC pin reset
Unused
Unused
Unused
Unused
Bit 6
LSB first/
addr incr
Reset
R counter
Lock detect counter
Ref freq
monitor
threshold
Enable
REF2
( REFIN )
frequency
monitor
Select
REF2
Enable
XTAL
OSC
Charge pump current
Bit 5
Soft reset
(self-
clearing)
Soft reset
(self-
clearing)
Reset
A and B
counters
Enable
REF1
(REFIN)
frequency
monitor
Use
REF_SEL
pin
Enable
clock
doubler
STATUS pin control
Rev. 0 | Page 61 of 84
EEPROM customer version ID (MSB)
EEPROM customer version ID (LSB)
14-bit R counter, Bits[7:0] (LSB)
13-bit B counter, Bits[7:0] (LSB)
Bit 4
Unused
Unused
Reset all
counters
Digital
lock
detect
window
Enable
automatic
reference
switchover
Disable
PLL status
register
R path delay
Unused
Reserved (read-only)
Reserved (read-only)
Unused
Unused
Bit 3
Unused
Unused
B counter
bypass
Disable
digital
lock detect
Stay on
REF2
Enable LD
pin
comparator
14-bit R counter, Bits[13:8] (MSB)
Charge pump mode
13-bit B counter, Bits[12:8] (MSB)
6-bit A counter
LD pin control
REFMON pin control
Bit 2
Soft reset
(self-
clearing)
Soft reset
(self-
clearing)
Enable
REF2
Unused
VCO calibration divider
Bit 1
LSB first/
addr incr
Enable
REF1
Enable
external
holdover
N path delay
Prescaler P
Antibacklash pulse width
PLL power-down
Unused
Bit 0 (LSB)
SDO active
Readback
active regs
VCO
calibration
now
Enable
differential
reference
Enable
holdover
AD9522-0
Default
Value
(Hex)
00
00
N/A
N/A
N/A
00
00
00
7D
01
00
00
03
00
06
00
06
00
00
00
00
80
00