AD9522-0BCPZ Analog Devices Inc, AD9522-0BCPZ Datasheet - Page 8
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AD9522-0BCPZ
Manufacturer Part Number
AD9522-0BCPZ
Description
12- Channel Clock Generator With Integra
Manufacturer
Analog Devices Inc
Type
Clock Generator, Fanout Distributionr
Datasheet
1.AD9522-0BCPZ-REEL7.pdf
(84 pages)
Specifications of AD9522-0BCPZ
Pll
Yes
Input
CMOS, LVDS, LVPECL
Output
CMOS, LVDS
Number Of Circuits
1
Ratio - Input:output
2:12, 2:24
Differential - Input:output
Yes/Yes
Frequency - Max
2.95GHz
Divider/multiplier
Yes/No
Voltage - Supply
3.135 V ~ 3.465 V
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
64-LFCSP
Frequency-max
2.8GHz
Operating Temperature (min)
-40C
Operating Temperature Classification
Industrial
Operating Temperature (max)
85C
Rad Hardened
No
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
AD9522-0BCPZ
Manufacturer:
Analog Devices Inc
Quantity:
135
Company:
Part Number:
AD9522-0BCPZ
Manufacturer:
AD
Quantity:
25
Part Number:
AD9522-0BCPZ
Manufacturer:
ADI/亚德诺
Quantity:
20 000
AD9522-0
TIMING CHARACTERISTICS
Table 5.
Parameter
LVDS OUTPUT RISE/FALL TIMES
PROPAGATION DELAY, t
OUTPUT SKEW, LVDS OUTPUTS
CMOS OUTPUT RISE/FALL TIMES
PROPAGATION DELAY, t
OUTPUT SKEW, CMOS OUTPUTS
OUTPUT SKEW, LVDS-TO-CMOS OUTPUT
1
Timing Diagrams
The output skew is the difference between any two similar delay paths while operating at the same voltage and temperature.
Output Rise Time, t
Output Fall Time, t
For All Divide Values
Variation with Temperature
LVDS Outputs That Share the Same Divider
LVDS Outputs on Different Dividers
All LVDS Outputs Across Multiple Parts
CMOS Outputs That Share the Same Divider
All CMOS Outputs on Different Dividers
Outputs That Share the Same Divider
Outputs That Are on Different Dividers
All CMOS Outputs Across Multiple Parts
Output Rise Time, t
Output Fall Time, t
For All Divide Values
Variation with Temperature
CLK
DIFFERENTIAL
20%
Figure 2. CLK/ CLK to Clock Output Timing, DIV = 1
t
CMOS
80%
t
Figure 3. LVDS Timing, Differential
t
LVDS
RP
FP
RP
FC
RC
LVDS
CMOS
t
, CLK-TO-LVDS OUTPUT
CLK
, CLK-TO-CMOS OUTPUT
LVDS
1
1
1
t
FP
Min
1866
1808
1913
−31
−193
Rev. 0 | Page 8 of 84
Typ
150
150
2313
2245
1
7
19
625
625
2400
2
10
27
+152
+160
Max
350
350
2812
2740
60
162
432
835
800
2950
55
230
500
+495
+495
Unit
ps
ps
ps
ps
ps/°C
ps
ps
ps
ps
ps
ps
ps/°C
ps
ps
ps
ps
ps
SINGLE-ENDED
20%
Figure 4. CMOS Timing, Single-Ended, 10 pF Load
Test Conditions/Comments
Termination = 100 Ω across differential pair
20% to 80%, measured differentially
80% to 20%, measured differentially
High frequency clock distribution configuration
Clock distribution configuration
Termination = 100 Ω across differential pair
Termination = open
20% to 80%; C
80% to 20%; C
Clock distribution configuration
All settings identical; different logic type
LVDS to CMOS on the same part
LVDS to CMOS on the same part
80%
t
RC
10pF LOAD
CMOS
LOAD
LOAD
= 10 pF
= 10 pF
t
FC