AD9522-0BCPZ Analog Devices Inc, AD9522-0BCPZ Datasheet - Page 17

• Manufacturer Part Number: AD9522-0BCPZ
• Description: 12- Channel Clock Generator With Integra
• Manufacturer: Analog Devices Inc
• Type: Clock Generator, Fanout Distributionr

Specifications of AD9522-0BCPZ

• Pll: Yes
• Input: CMOS, LVDS, LVPECL
• Output: CMOS, LVDS
• Number Of Circuits: 1
• Ratio - Input:output: 2:12, 2:24
• Differential - Input:output: Yes/Yes
• Frequency - Max: 2.95GHz
• Divider/multiplier: Yes/No
• Voltage - Supply: 3.135 V ~ 3.465 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 64-LFCSP
• Frequency-max: 2.8GHz
• Operating Temperature (min): -40C
• Operating Temperature Classification: Industrial
• Operating Temperature (max): 85C
• Rad Hardened: No
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
Table 21. Pin Function Descriptions
Pin No.
1, 11, 12, 27,
32, 35, 40,
41, 46, 49,
54, 57, 60, 61
2
3
4
5
6
7
8
9
10
13
14
Input/
Output
I
O
O
I
O
O
I
I
I
O
I
I
Pin
Type
Power
3.3 V CMOS
3.3 V CMOS
Power
Loop filter
3.3 V CMOS
3.3 V CMOS
3.3 V CMOS
Loop filter
Loop filter
Differential
clock input
Differential
clock input
SCLK/SCL
NOTES
1. EXPOSED DIE PAD MUST BE CONNECTED TO GND.
REF_SEL
REFMON
BYPASS
STATUS
SYNC
Mnemonic
VS
REFMON
LD
VCP
CP
STATUS
REF_SEL
SYNC
LF
BYPASS
CLK
CLK
VCP
CLK
CLK
CP
CS
VS
LD
VS
VS
LF
10
11
12
13
14
15
16
1
2
3
4
5
6
7
8
9
PIN 1
INDICATOR
Figure 5. Pin Configuration
Description
3.3 V Power Pins.
Reference Monitor (Output). This pin has multiple selectable outputs.
Lock Detect (Output). This pin has multiple selectable outputs.
Power Supply for Charge Pump (CP); VS < VCP < 5.0 V. VCP must still be connected
to 3.3 V if the PLL is not used.
Charge Pump (Output). This pin connects to an external loop filter. This pin can
be left unconnected if the PLL is not used.
Programmable Status Output.
Reference Select. It selects REF1 (low) or REF2 (high). This pin has an internal
30 kΩ pull-down resistor.
Manual Synchronizations and Manual Holdover. This pin initiates a manual
synchronization and is used for manual holdover. Active low. This pin has an
internal 30 kΩ pull-up resistor.
Loop Filter (Input). It connects internally to the VCO control voltage node.
This pin is for bypassing the LDO to ground with a 220 nF capacitor.
This pin can be left unconnected if the PLL is not used.
Along with CLK, this pin is the differential input for the clock distribution section.
Along with CLK, this pin is the differential input for the clock distribution section. If a
single-ended input is connected to the CLK pin, connect a 0.1 μF bypass capacitor
from this pin to ground.
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(Not to Scale)
AD9522
TOP VIEW
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
OUT3 (OUT3A)
OUT3 (OUT3B)
VS
OUT4 (OUT4A)
OUT4 (OUT4B)
OUT5 (OUT5A)
OUT5 (OUT5B)
VS
VS
OUT8 (OUT8B)
OUT8 (OUT8A)
OUT7 (OUT7B)
OUT7 (OUT7A)
VS
OUT6 (OUT6B)
OUT6 (OUT6A)
AD9522-0