AD9522-0BCPZ Analog Devices Inc, AD9522-0BCPZ Datasheet - Page 34

• Manufacturer Part Number: AD9522-0BCPZ
• Description: 12- Channel Clock Generator With Integra
• Manufacturer: Analog Devices Inc
• Type: Clock Generator, Fanout Distributionr

Specifications of AD9522-0BCPZ

• Pll: Yes
• Input: CMOS, LVDS, LVPECL
• Output: CMOS, LVDS
• Number Of Circuits: 1
• Ratio - Input:output: 2:12, 2:24
• Differential - Input:output: Yes/Yes
• Frequency - Max: 2.95GHz
• Divider/multiplier: Yes/No
• Voltage - Supply: 3.135 V ~ 3.465 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 64-LFCSP
• Frequency-max: 2.8GHz
• Operating Temperature (min): -40C
• Operating Temperature Classification: Industrial
• Operating Temperature (max): 85C
• Rad Hardened: No
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

AD9522-0
Charge Pump (CP)
The charge pump is controlled by the PFD. The PFD monitors
the phase and frequency relationship between its two inputs and
tells the CP to pump up or pump down to charge or discharge the
integrating node (part of the loop filter). The integrated and
filtered CP current is transformed into a voltage that drives the
tuning node of the internal VCO through the LF pin (or the
tuning pin of an external VCO) to move the VCO frequency up
or down. The CP can be set (0x010[3:2]) for high impedance
(allows holdover operation), for normal operation (attempts to
lock the PLL loop), for pump-up, or for pump-down (test modes).
The CP current is programmable in eight steps from (nominally)
0.6 mA to 4.8 mA. The exact value of the CP current LSB is set
by the CPRSET resistor, which is nominally 5.1 kΩ.
On-Chip VCO
The AD9522 includes an on-chip VCO covering the frequency
range shown in Table 2. Achieving low VCO phase noise was a
priority in the design of the VCO.
To tune over the wide range of frequencies covered by this
VCO, tuning ranges are used. The calibration procedure selects
the correct range for the desired VCO frequency. See the VCO
Calibration section for additional information.
The on-chip VCO is powered by an on-chip, low dropout (LDO),
linear voltage regulator. The LDO provides some isolation of
the VCO from variations in the power supply voltage level.
The BYPASS pin should be connected to ground by a 220 nF
capacitor to ensure stability. This LDO employs the same
technology used in the anyCAP® line of regulators from Analog
Devices, Inc., making it insensitive to the type of capacitor used.
Driving an external load from the BYPASS pin is not supported.
When an external VCO/VCXO is use, the BYPASS and LF pins
should be left floating. This configuration is shown in Figure 42.
PLL External Loop Filter
When an internal VCO is used, the external loop filter should
be referenced to the BYPASS pin for optimal noise and spurious
performance. An example of an external loop filter for a PLL
that uses the internal VCO is shown in Figure 41. A loop filter
must be calculated for each desired PLL configuration. The values
of the components depend upon the VCO frequency, the K
the PFD frequency, the CP current, the desired loop bandwidth,
and the desired phase margin. The loop filter affects the phase
noise, the loop settling time, and the loop stability. A basic
knowledge of PLL theory is helpful for understanding loop filter
design. ADIsimCLK can help with the calculation of a loop
filter according to the application requirements.
When an external VCO is used, the external loop filter should
be referenced to ground. An example of an external loop filter
for a PLL using an external VCO is shown in Figure 42.
VCO
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PLL Reference Inputs
The AD9522 features a flexible PLL reference input circuit that
allows a fully differential input, two separate single-ended inputs,
or a 16.67 MHz to 33.33 MHz crystal oscillator with an on-chip
maintaining amplifier. An optional reference clock doubler
can be used to double the PLL reference frequency. The input
frequency range for the reference inputs is specified in Table 2.
Both the differential and the single-ended inputs are self-biased,
allowing for easy ac coupling of input signals.
Either a differential or a single-ended reference must be specifically
enabled. All PLL reference inputs are off by default.
The differential input and the single-ended inputs share two pins,
REFIN (REF1) and REFIN (REF2). The desired reference input
type is selected and controlled by 0x01C (see
When the differential reference input is selected, the self-bias
level of the two sides is offset slightly to prevent chattering of
the input buffer when the reference is slow or missing. The
specification for this voltage level can be found in Table 2.
The input hysteresis increases the voltage swing required of
the driver to overcome the offset.
The single-ended inputs can be driven by either a dc-coupled
CMOS level signal or an ac-coupled sine wave or square wave.
To avoid input buffer chatter when a single-ended, ac-coupled
input signal stops toggling, the user can set 0x018[7] to 1b. This
shifts the dc offset bias point down 140 mV. To increase isolation
and reduce power, each single-ended input can be independently
powered down.
The differential reference input receiver is powered down when
it is not selected or when the PLL is powered down. The single-
ended buffers power down when the PLL is powered down or
when their respective individual power-down registers are set.
When the differential mode is selected, the single-ended inputs
are powered down.
Figure 41. Example of External Loop Filter for a PLL Using the Internal VCO
Figure 42. Example of External Loop Filter for a PLL Using an External VCO
AD9522
AD9522
CHARGE
CHARGE
PUMP
PUMP
VCO
LF
CP
BYPASS
CLK/CLK
CP
C
BP
= 220nF
C1
C1
EXTERNAL
VCO/VCXO
R1
R1
C2
Table 48
C2
R2
R2
C3
C3
and
Table 52
).