AD9522-0BCPZ Analog Devices Inc, AD9522-0BCPZ Datasheet - Page 78

• Manufacturer Part Number: AD9522-0BCPZ
• Description: 12- Channel Clock Generator With Integra
• Manufacturer: Analog Devices Inc
• Type: Clock Generator, Fanout Distributionr

Specifications of AD9522-0BCPZ

• Pll: Yes
• Input: CMOS, LVDS, LVPECL
• Output: CMOS, LVDS
• Number Of Circuits: 1
• Ratio - Input:output: 2:12, 2:24
• Differential - Input:output: Yes/Yes
• Frequency - Max: 2.95GHz
• Divider/multiplier: Yes/No
• Voltage - Supply: 3.135 V ~ 3.465 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 64-LFCSP
• Frequency-max: 2.8GHz
• Operating Temperature (min): -40C
• Operating Temperature Classification: Industrial
• Operating Temperature (max): 85C
• Rad Hardened: No
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Reg.
Addr
(Hex) Bit(s) Name
1E1
1E1
1E1
1E1
AD9522-0
Table 56. System
Reg.
Addr
(Hex) Bit(s) Name
230
230
230
230
Table 57. Update All Registers
Reg.
Addr
(Hex) Bit(s) Name
232
[3]
[2]
[1]
[0]
[0]
[3]
[2]
[1]
[0]
Power-down VCO clock interface Powers down the interface block between VCO and clock distribution.
Power-down VCO and CLK
Select VCO or CLK
Bypass VCO divider
IO_UPDATE
Disable power-on SYNC
Power-down SYNC
Power-down distribution reference
Soft SYNC
This bit must be set to 1 to transfer the contents of the buffer registers into the active registers. This happens
on the next SCLK rising edge. This bit is self-clearing; that is, it does not have to be set back to 0.
[0] = 1 (self-clearing); update all active registers to the contents of the buffer registers.
Description
Description
[3] = 0; normal operation (default).
[3] = 1; power down.
Powers down both the CLK input and VCO.
[2] = 0; normal operation (default).
[2] = 1; power down.
Selects either the VCO or the CLK as the input to VCO divider.
[1] = 0; select external CLK as input to VCO divider (default).
[1] = 1; select VCO as input to the VCO divider; cannot bypass the VCO divider when this
is selected. This bit must be set to use the PLL with the internal VCO.
Bypasses or uses the VCO divider.
[0] = 0; use the VCO divider (default).
[0] = 1; bypass the VCO divider; cannot select VCO as input when this is selected.
Description
Power-on SYNC mode. Used to disable the antiruntpulse circuitry.
[3] = 0; enable the antiruntpulse circuitry (default).
[3] = 1; disable the antiruntpulse circuitry.
Powers down the SYNC function.
[2] = 0; normal operation of the SYNC function (default).
[2] = 1; power-down SYNC circuitry.
Powers down the reference for the distribution section.
[1] = 0; normal operation of the reference for the distribution section (default).
[1] = 1; powers down the reference for the distribution section.
The soft SYNC bit works the same as the SYNC pin, except that the polarity of the bit
is reversed; that is, a high level forces selected channels into a predetermined static
state, and a 1-to-0 transition triggers a SYNC.
[0] = 0; same as SYNC high.
[0] = 1; same as SYNC low.
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