AD9522-0BCPZ Analog Devices Inc, AD9522-0BCPZ Datasheet - Page 80

• Manufacturer Part Number: AD9522-0BCPZ
• Description: 12- Channel Clock Generator With Integra
• Manufacturer: Analog Devices Inc
• Type: Clock Generator, Fanout Distributionr

Specifications of AD9522-0BCPZ

• Pll: Yes
• Input: CMOS, LVDS, LVPECL
• Output: CMOS, LVDS
• Number Of Circuits: 1
• Ratio - Input:output: 2:12, 2:24
• Differential - Input:output: Yes/Yes
• Frequency - Max: 2.95GHz
• Divider/multiplier: Yes/No
• Voltage - Supply: 3.135 V ~ 3.465 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 64-LFCSP
• Frequency-max: 2.8GHz
• Operating Temperature (min): -40C
• Operating Temperature Classification: Industrial
• Operating Temperature (max): 85C
• Rad Hardened: No
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

AD9522-0
APPLICATIONS INFORMATION
FREQUENCY PLANNING USING THE AD9522
The AD9522 is a highly flexible PLL. When choosing the PLL
settings and version of the AD9522, the following guidelines
should be kept in mind.
The AD9522 has four frequency dividers: the reference (or R)
divider, the feedback (or N) divider, the VCO divider, and the
channel divider. When trying to achieve a particularly difficult
frequency divide ratio requiring a large amount of frequency
division, some of the frequency division can be done by either
the VCO divider or the channel divider, thus allowing a higher
phase detector frequency and more flexibility in choosing the
loop bandwidth.
Within the AD9522 family, lower VCO frequencies generally
result in slightly better jitter. The difference in integrated jitter
(from 12 kHz to 20 MHz offset) for the same output frequency is
usually less than 150 fs over the entire VCO frequency range
(1.4 GHz to 2.95 GHz) of the AD9522 family. If the desired
frequency plan can be achieved with a version of the AD9522
that has a lower VCO frequency, choosing the lower frequency
part results in the best phase noise and the lowest jitter. However,
choosing a higher VCO frequency can result in more flexibility
in frequency planning.
Choosing a nominal charge pump current in the middle of the
allowable range as a starting point allows the designer to increase or
decrease the charge pump current, and thus allows the designer
to fine-tune the PLL loop bandwidth in either direction.
ADIsimCLK is a powerful PLL modeling tool that can be
downloaded from
for determining the optimal loop filter for a given application.
USING THE AD9522 OUTPUTS FOR ADC CLOCK
APPLICATIONS
Any high speed ADC is extremely sensitive to the quality of the
sampling clock of the AD9522. An ADC can be thought of as a
sampling mixer, and any noise, distortion, or time jitter on the
clock is combined with the desired signal at the analog-to-
digital output. Clock integrity requirements scale with the analog
input frequency and resolution, with higher analog input
frequency applications at ≥14-bit resolution being the most
stringent. The theoretical SNR of an ADC is limited by the ADC
resolution and the jitter on the sampling clock. Considering an
ideal ADC of infinite resolution where the step size and
quantization error can be ignored, the available SNR can be
expressed approximately by
where:
f
t
A
J
is the rms jitter on the sampling clock.
is the highest analog frequency being digitized.
SNR
(dB)
=
20log
www.analog.com
⎛
⎜
⎜
⎝
2
π
f
1
A
t
J
⎞
⎟
⎟
⎠
and is a very accurate tool
Rev. 0 | Page 80 of 84
Figure 70 shows the required sampling clock jitter as a function
of the analog frequency and effective number of bits (ENOB).
See the AN-756 Application Note and the AN-501 Application
Note at www.analog.com.
Many high performance ADCs feature differential clock inputs
to simplify the task of providing the required low jitter clock on
a noisy PCB. Distributing a single-ended clock on a noisy PCB
can result in coupled noise on the sampling clock. Differential
distribution has inherent common-mode rejection that can
provide superior clock performance in a noisy environment.
The differential LVDS outputs of the AD9522 enable clock
solutions that maximize converter SNR performance.
The input requirements of the ADC (differential or single-
ended, logic level termination) should be considered when
selecting the best clocking/converter solution. In some cases,
the LVPECL outputs of the AD9520 may be desirable for
clocking a converter instead of the AD9522’s LVDS outputs.
LVDS CLOCK DISTRIBUTION
The AD9522 provides clock outputs that are selectable as either
CMOS or LVDS level outputs. LVDS is a differential output
option that uses a current mode output stage. The nominal
current is 3.5 mA, which yields 350 mV output swing across a
100 Ω resistor. An output current of 7 mA is also available in
cases where a larger output swing is required. The LVDS output
meets or exceeds all ANSI/TIA/EIA-644 specifications.
110
100
90
80
70
60
50
40
30
10
Figure 70. SNR and ENOB vs. Analog Input Frequency
f
A
100
(MHz)
SNR = 20log
2πf
1
A
t
J
1k
18
16
14
12
10
8
6