AD9522-0BCPZ Analog Devices Inc, AD9522-0BCPZ Datasheet - Page 45

• Manufacturer Part Number: AD9522-0BCPZ
• Description: 12- Channel Clock Generator With Integra
• Manufacturer: Analog Devices Inc
• Type: Clock Generator, Fanout Distributionr

Specifications of AD9522-0BCPZ

• Pll: Yes
• Input: CMOS, LVDS, LVPECL
• Output: CMOS, LVDS
• Number Of Circuits: 1
• Ratio - Input:output: 2:12, 2:24
• Differential - Input:output: Yes/Yes
• Frequency - Max: 2.95GHz
• Divider/multiplier: Yes/No
• Voltage - Supply: 3.135 V ~ 3.465 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 64-LFCSP
• Frequency-max: 2.8GHz
• Operating Temperature (min): -40C
• Operating Temperature Classification: Industrial
• Operating Temperature (max): 85C
• Rad Hardened: No
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Duty-cycle correction requires the following channel divider
conditions:
•
•
When not bypassed or corrected by the DCC function, the duty
cycle of each channel divider output is the numerical value of
(N + 1)/(N + M + 2) expressed as a percent.
The duty cycle at the output of the channel divider for various
configurations is shown in Table 34 to Table 37.
Table 34. Channel Divider Output Duty Cycle with VCO
Divider ≠ 1, Input Duty Cycle Is 50%
VCO
Divider
Even
Odd = 3
Odd = 5
Even, odd
Even, odd
Table 35. Channel Divider Output Duty Cycle with VCO
Divider ≠ 1, Input Duty Cycle Is X%
VCO
Divider
Even
Odd = 3
Odd = 5
Even
Even
Odd = 3
Odd = 3
Odd = 5
Odd = 5
An even division must be set as M = N.
An odd division must be set as M = N + 1.
N + M + 2
Channel
divider
bypassed
Channel
divider
bypassed
Channel
divider
bypassed
Even
Odd
Even
Odd
Even
Odd
N + M + 2
Channel
divider
bypassed
Channel
divider
bypassed
Channel
divider
bypassed
Even
Odd
D
X
D
X
Disable Div
DCC = 1
50%
33.3%
40%
(N + 1)/
(N + M + 2)
(N + 1)/
(N + M + 2)
(N + 1)/
(N + M + 2)
(N + 1)/
(N + M + 2)
(N + 1)/
(N + M + 2)
(N + 1)/
(N + M + 2)
Disable Div
DCC = 1
50%
33.3%
40%
(N + 1)/(N + M + 2)
(N + 1)/(N + M + 2)
Output Duty Cycle
Output Duty Cycle
Disable Div DCC = 0
50%
(1 + X%)/3
(2 + X%)/5
50%, requires M = N
50%, requires M = N + 1
50%, requires M = N
(3N + 4 + X%)/(6N + 9),
requires M = N + 1
50%, requires M = N
(5N + 7 + X%)/(10N + 15),
requires M = N + 1
Disable Div
DCC = 0
50%
50%
50%
50%, requires
M = N
50%, requires
M = N + 1
Rev. 0 | Page 45 of 84
Divider
0
1
2
3
Table 36. Channel Divider Output Duty Cycle When the
VCO Divider Is Enabled and Set to 1
Input
Clock
Duty Cycle
Any
50%
X%
Note that the channel divider must be enabled when the VCO
divider = 1.
Table 37. Channel Divider Output Duty Cycle When the
VCO Divider Is Bypassed
Input
Clock
Duty Cycle
Any
Any
50%
X%
The internal VCO has a duty cycle of 50%. Therefore, when the
VCO divider equals one, the duty cycle is 50%. If the CLK input
is routed directly to the output, the duty cycle of the output is the
same as the CLK input.
Phase Offset or Coarse Time Delay
Each channel divider allows for a phase offset, or a coarse time
delay, to be programmed by setting register bits (see Table 38).
These settings determine the number of cycles (successive rising
edges) of the channel divider input frequency by which to offset, or
delay, the rising edge of the output of the divider. This delay is
with respect to a nondelayed output (that is, with a phase offset
of zero). The amount of the delay is set by five bits loaded into
the phase offset (PO) register plus the start high (SH) bit for
each channel divider. When the start high bit is set, the delay is
also affected by the number of low cycles (M) programmed for
the divider.
It is necessary to use the SYNC function to make phase offsets
effective (see the Synchronizing the Outputs— Function section).
Table 38. Setting Phase Offset and Division
Start
High (SH)
0x191[4]
0x194[4]
0x197[4]
0x19A[4]
N + M + 2
Even
Odd
Odd
N + M + 2
Channel
divider
bypassed
Even
Odd
Odd
D
D
X
X
Phase
Offset (PO)
0x191[3:0]
0x194[3:0]
0x197[3:0]
0x19A[3:0]
Disable Div
DCC = 1
(N + 1)/
(M + N + 2)
(N + 1)/
(M + N + 2)
(N + 1)/
(M + N + 2)
Disable Div
DCC = 1
Same as input
duty cycle
(N + 1)/
(M + N + 2)
(N + 1)/
(M + N + 2)
(N + 1)/
(M + N + 2)
Output Duty Cycle
Output Duty Cycle
Low Cycles
M
0x190[7:4]
0x193[7:4]
0x196[7:4]
0x199[7:4]
Disable Div DCC = 0
50%, requires M = N
50%, requires M = N + 1
(N + 1 + X%)/(2 × N + 3),
requires M = N + 1
Disable Div DCC = 0
Same as input duty
cycle
50%, requires M = N
50%, requires M = N + 1
(N + 1 + X%)/(2 × N + 3),
requires M = N + 1
AD9522-0
High Cycles
N
0x190[3:0]
0x193[3:0]
0x196[3:0]
0x199[3:0]