AD9522-0BCPZ Analog Devices Inc, AD9522-0BCPZ Datasheet - Page 42

• Manufacturer Part Number: AD9522-0BCPZ
• Description: 12- Channel Clock Generator With Integra
• Manufacturer: Analog Devices Inc
• Type: Clock Generator, Fanout Distributionr

Specifications of AD9522-0BCPZ

• Pll: Yes
• Input: CMOS, LVDS, LVPECL
• Output: CMOS, LVDS
• Number Of Circuits: 1
• Ratio - Input:output: 2:12, 2:24
• Differential - Input:output: Yes/Yes
• Frequency - Max: 2.95GHz
• Divider/multiplier: Yes/No
• Voltage - Supply: 3.135 V ~ 3.465 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 64-LFCSP
• Frequency-max: 2.8GHz
• Operating Temperature (min): -40C
• Operating Temperature Classification: Industrial
• Operating Temperature (max): 85C
• Rad Hardened: No
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

AD9522-0
ZERO DELAY OPERATION
Zero delay operation aligns the phase of the output clocks with
the phase of the external PLL reference input. There are two
zero delay modes on the AD9522: internal and external.
Internal Zero Delay Mode
The internal zero delay function of the AD9522 is achieved by
feeding the output of Channel Divider 0 back to the PLL N
divider. In Figure 49, the change in signal routing for internal
zero delay mode is shown in blue.
Set Register 0x01E[2:1] = 01b to select internal zero delay mode.
In the internal zero delay mode, the output of Channel Divider
0 is routed back to the PLL (N divider) through Mux3 and
Mux1 (feedback path shown in blue in Figure 49). The PLL
synchronizes the phase/edge of the output of Channel Divider 0
with the phase/edge of the reference input.
Because the channel dividers are synchronized to each other,
the outputs of the channel divider are synchronous with the
reference input. Both the R delay and the N delay inside the
PLL can be programmed to compensate for the propagation
delay from the output drivers and PLL components to minimize
the phase offset between the clock output and the reference
input to achieve zero delay.
CLK/CLK
REFIN/
REFIN
LF
MUX1
2, 3, 4, 5, OR 6
DIVIDE BY 1,
1
0
DIVIDER
DIVIDER
REG 0x01E[1] = 1
ZERO DELAY FEEDBACK CLOCK
R
N
DELAY
DELAY
R
N
Figure 49. Zero Delay Function
Rev. 0 | Page 42 of 84
PFD
CP
REG 0x01E[0]
External Zero Delay Mode
The external zero delay function of the AD9522 is achieved by
feeding one clock output back to the CLK input and ultimately
back to the PLL N divider. In Figure 49, the change in signal
routing for external zero delay mode is shown in red.
Setting 0x01E[2:1] = 11b to select the external zero delay mode.
In external zero delay mode, one of the twelve output clocks
(OUT0 to OUT11) can be routed back to the PLL (N divider)
through the CLK/ CLK pins and through Mux3 and Mux1. This
feedback path is shown in red in
The user must specify which channel divider will be used for
external zero delay mode in order for VCO calibration to work
correctly. Channel Divider 0 is the default. Channel Divider 1,
Channel Divider 2, or Channel Divider 3 can be selected for zero
delay feedback by changing the value in Register 0x01E[4:3].
The PLL synchronizes the phase/edge of the feedback output clock
with the phase/edge of the reference input. Because the channel
dividers are synchronized to each other, the clock outputs are
synchronous with the reference input. Both the R delay and the
N delay inside the PLL can be programmed to compensate for
the propagation delay from the PLL components to minimize the
phase offset between the feedback clock and the reference input.
INTERNAL FEEDBACK PATH
EXTERNAL FEEDBACK PATH
ZERO DELAY
CHANNEL DIVIDER 0
CHANNEL DIVIDER 1
CHANNEL DIVIDER 2
CHANNEL DIVIDER 3
AD9522
Figure 49
OUT0 TO OUT2
OUT3 TO OUT5
OUT6 TO OUT8
OUT9 TO OUT11
.
FILTER
LOOP