ADUC836BSZ Analog Devices Inc, ADUC836BSZ Datasheet - Page 32

• Manufacturer Part Number: ADUC836BSZ
• Description: 16bit Dual ADC With Embedded 8 Bit MCU
• Manufacturer: Analog Devices Inc
• Series: MicroConverter® ADuC8xxr

Specifications of ADUC836BSZ

• Core Processor: 8052
• Core Size: 8-Bit
• Speed: 12.58MHz
• Connectivity: EBI/EMI, I²C, SPI, UART/USART
• Peripherals: POR, PSM, PWM, Temp Sensor, WDT
• Number Of I /o: 34
• Program Memory Size: 62KB (62K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 4K x 8
• Ram Size: 2.25K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.25 V
• Data Converters: A/D 7x16b; D/A 1x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 52-MQFP, 52-PQFP
• Cpu Family: ADuC8xx
• Device Core: 8052
• Device Core Size: 8b
• Frequency (max): 12.58MHz
• Interface Type: I2C/SPI/UART
• Total Internal Ram Size: 2.25KB
• # I/os (max): 26
• Number Of Timers - General Purpose: 3
• Operating Supply Voltage (typ): 3.3/5V
• Operating Supply Voltage (max): 5.25V
• Operating Supply Voltage (min): 2.7V
• On-chip Adc: 2(2-chx16-bit)
• On-chip Dac: 1-chx12-bit
• Instruction Set Architecture: CISC
• Operating Temp Range: -40C to 125C
• Operating Temperature Classification: Automotive
• Mounting: Surface Mount
• Pin Count: 52
• Package Type: MQFP
• Package: 52MQFP
• Family Name: ADuC8xx
• Maximum Speed: 12.58 MHz
• Operating Supply Voltage: 3.3|5 V
• Data Bus Width: 8 Bit
• Number Of Programmable I/os: 26
• Number Of Timers: 3
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Using the Flash/EE Data Memory
The 4 Kbytes of Flash/EE data memory are configured as
1024 pages, each of four bytes. As with the other ADuC836
peripherals, the interface to this memory space is via a group of
registers mapped in the SFR space. A group of four data regis-
ters (EDATA1–A4) is used to hold the four bytes of data at each
page. The page is addressed via the two registers EADRH and
EADRL. Finally, ECON is an 8-bit control register that may be
written with one of nine Flash/EE memory access commands to
trigger various read, write, erase, and verify functions.
A block diagram of the SFR interface to the Flash/EE data
memory array is shown in Figure 20.
ECON—Flash/EE Memory Control SFR
Programming of either the Flash/EE data memory or the Flash/EE
program memory is done through the Flash/EE Memory Control
SFR (ECON). This SFR allows the user to read, write, erase, or
verify the 4 Kbytes of Flash/EE data memory or the 56 Kbytes of
Flash/EE program memory.
ECON Value
01H
READ
02H
WRITE
03H
04H
VERIFY
05H
ERASE PAGE
06H
ERASE ALL
81H
READBYTE
82H
WRITEBYTE
0FH
EXULOAD
F0H
ULOAD
ADuC836
Command Description
(Normal Mode) (Power-On Default)
Results in four bytes in the Flash/EE data memory,
addressed by the page address EADRH/L, being read
into EDATA 1 to 4.
Results in four bytes in EDATA1–A4 being written to the Results in bytes 0–255 of internal XRAM being written
Flash/EE data memory, at the page address given by
EADRH/L (0  EADRH/L < 0400H)
Note: The four bytes in the page being addressed must
be pre-erased.
Reserved Command
Verifies if the data in EDATA1–4 is contained in the
page address given by EADRH/L. A subsequent read
of the ECON SFR will result in a 0 being read if the
verification is valid, or a nonzero value being read
to indicate an invalid verification.
Results in the erase of the 4-bytes page of Flash/EE
data memory addressed by the page address EADRH/L
Results in the erase of entire four Kbytes of Flash/EE
data memory.
Results in the byte in the Flash/EE data memory,
addressed by the byte address EADRH/L, being read
into EDATA1. (0  EADRH/L  0FFFH).
Results in the byte in EDATA1 being written into
Flash/EE data memory, at the byte address EADRH/L.
Leaves the ECON instructions to operate on the
Flash/EE data memory.
Enters ULOAD mode, directing subsequent ECON
instructions to operate on the Flash/EE program memory.
Table XIV. ECON—Flash/EE Memory Commands
–32–
Figure 20. Flash/EE Data Memory Control and Configuration
ARE GIVEN IN
ADDRESSES
BRACKETS
BYTE
3FFH
3FEH
03H
02H
01H
00H
Command Description
(ULOAD Mode)
Not Implemented. Use the MOVC instruction.
to the 256 bytes of Flash/EE program memory at the
page address given by EADRH. (0  EADRH < E0H)
Note: The 256 bytes in the page being addressed must
be pre-erased.
Reserved Command
Not Implemented. Use the MOVC and MOVX
instructions to verify the WRITE in software.
Results in the 64-byte page of Flash/EE program
memory, addressed by the byte address EADRH/L
being erased. EADRL can equal any of 64 locations
within the page. A new page starts whenever EADRL
is equal to 00H, 40H, 80H, or C0H.
Results in the erase of the entire 56 Kbytes of ULOAD
Flash/EE program memory.
Not Implemented. Use the MOVC command.
Results in the byte in EDATA1 being written into
Flash/EE program memory at the byte address
EADRH/L (0  EADRH/L  DFFFH).
Enters Normal mode, directing subsequent ECON
instructions to operate on the Flash/EE data memory.
Leaves the ECON instructions to operate on the Flash/EE
program memory.
(0FFCH)
(0FF8H)
(0008H)
(0004H)
(0000H)
BYTE 1
BYTE 1
(000CH)
BYTE 1
BYTE 1
BYTE 1
BYTE 1
(0FFDH)
(0FF9H)
(000DH)
(0009H)
(0005H)
(0001H)
BYTE 2
BYTE 2
BYTE 2
BYTE 2
BYTE 2
BYTE 2
(000EH)
(000AH)
(0FFEH)
(0FFAH)
(0006H)
(0002H)
BYTE 3
BYTE 3
BYTE 3
BYTE 3
BYTE 3
BYTE 3
(0FFFH)
(0FFBH)
(000BH)
BYTE 4
BYTE 4
(000FH)
BYTE 4
BYTE 4
(0007H)
(0003H)
BYTE 4
BYTE 4
REV. A