ADUC836BSZ Analog Devices Inc, ADUC836BSZ Datasheet - Page 36

16bit Dual ADC With Embedded 8 Bit MCU

ADUC836BSZ

Manufacturer Part Number
ADUC836BSZ
Description
16bit Dual ADC With Embedded 8 Bit MCU
Manufacturer
Analog Devices Inc
Series
MicroConverter® ADuC8xxr
Datasheet

Specifications of ADUC836BSZ

Core Processor
8052
Core Size
8-Bit
Speed
12.58MHz
Connectivity
EBI/EMI, I²C, SPI, UART/USART
Peripherals
POR, PSM, PWM, Temp Sensor, WDT
Number Of I /o
34
Program Memory Size
62KB (62K x 8)
Program Memory Type
FLASH
Eeprom Size
4K x 8
Ram Size
2.25K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.25 V
Data Converters
A/D 7x16b; D/A 1x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Package / Case
52-MQFP, 52-PQFP
Cpu Family
ADuC8xx
Device Core
8052
Device Core Size
8b
Frequency (max)
12.58MHz
Interface Type
I2C/SPI/UART
Total Internal Ram Size
2.25KB
# I/os (max)
26
Number Of Timers - General Purpose
3
Operating Supply Voltage (typ)
3.3/5V
Operating Supply Voltage (max)
5.25V
Operating Supply Voltage (min)
2.7V
On-chip Adc
2(2-chx16-bit)
On-chip Dac
1-chx12-bit
Instruction Set Architecture
CISC
Operating Temp Range
-40C to 125C
Operating Temperature Classification
Automotive
Mounting
Surface Mount
Pin Count
52
Package Type
MQFP
Package
52MQFP
Family Name
ADuC8xx
Maximum Speed
12.58 MHz
Operating Supply Voltage
3.3|5 V
Data Bus Width
8 Bit
Number Of Programmable I/os
26
Number Of Timers
3
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

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PULSEWIDTH MODULATOR (PWM)
The PWM on the ADuC836 is a highly flexible PWM offering
programmable resolution and input clock, and can be configured
for any one of six different modes of operation.Two of these modes
allow the PWM to be configured as a - DAC with up to 16 bits
of resolution. A block diagram of the PWM is shown in Figure 26.
ADuC836
32.768kHz/15
12.583MHz
32.768kHz
PWM
CLK
Figure 26. PWM Block Diagram
Bit
7
6
5
4
3
2
1
0
SELECT
CLOCK
Name
–––
MD2
MD1
MD0
CDIV1
CDIV0
CSEL1
CSEL0
MODE
16-BIT PWM COUNTER
PROGRAMMABLE
COMPARE
PWM0H/L
DIVIDER
Description
Reserved for Future Use
PWM Mode Bits
The MD2/1/0 bits choose the PWM mode as follows:
MD2
0
0
0
0
1
1
1
1
PWM Clock Divider.
Scale the clock source for the PWM counter as follows:
CDIV1 CDIV0
0
0
1
1
PWM Clock Divider.
Select the clock source for the PWM as follows:
CSEL1 CSEL0
0
0
1
1
Table XVI. PWMCON SFR Bit Designations
PWM1H/L
MD1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
P1.0
P1.1
MD0
0
1
0
1
0
1
0
1
Description
PWM Counter = Selected Clock/1
PWM Counter = Selected Clock 4
PWM Counter = Selected Clock/16
PWM Counter = Selected Clock/64
Description
PWM Clock = f
PWM Clock = f
PWM Clock = External Input at P3.4/T0/PWMCLK
PWM Clock = f
–36–
The PWM uses five SFRs: the control SFR, PWMCON, and
four data SFRs: PWM0H, PWM0L, PWM1H, and PWM1L.
PWMCON (as described in Table XVI) controls the different
modes of operation of the PWM as well as the PWM clock fre-
quency. PWM0H/L and PWM1H/L are the data registers that
determine the duty cycles of the PWM outputs at P1.0 and P1.1.
To use the PWM user software, first write to PWMCON to select
the PWM mode of operation and the PWM input clock. Writing
to PWMCON also resets the PWM counter. In any of the 16-bit
modes of operation (modes 1, 3, 4, 6), user software should write
to the PWM0L or PWM1L SFRs first. This value is written to a
hidden SFR. Writing to the PWM0H or PWM1H SFRs updates
both the PWMxH and the PWMxL SFRs but does not change
the outputs until the end of the PWM cycle in progress. The
values written to these 16-bit registers are then used in the next
PWM cycle.
PWMCON
SFR Address
Power-On Default Value
Bit Addressable
Mode
Mode 0: PWM Disabled
Mode 1: Single Variable Resolution PWM
Mode 2: Twin 8-bit PWM
Mode 3: Twin 16-bit PWM
Mode 4: Dual NRZ 16-bit - DAC
Mode 5: Dual 8-bit PWM
Mode 6: Dual RZ 16-bit - DAC
Reserved for Future Use
XTAL
XTAL
VCO
(12.58 MHz)
/15
PWM Control SFR
AEH
00H
No
REV. A

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