ADUC836BSZ Analog Devices Inc, ADUC836BSZ Datasheet - Page 33

• Manufacturer Part Number: ADUC836BSZ
• Description: 16bit Dual ADC With Embedded 8 Bit MCU
• Manufacturer: Analog Devices Inc
• Series: MicroConverter® ADuC8xxr

Specifications of ADUC836BSZ

• Core Processor: 8052
• Core Size: 8-Bit
• Speed: 12.58MHz
• Connectivity: EBI/EMI, I²C, SPI, UART/USART
• Peripherals: POR, PSM, PWM, Temp Sensor, WDT
• Number Of I /o: 34
• Program Memory Size: 62KB (62K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 4K x 8
• Ram Size: 2.25K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.25 V
• Data Converters: A/D 7x16b; D/A 1x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 52-MQFP, 52-PQFP
• Cpu Family: ADuC8xx
• Device Core: 8052
• Device Core Size: 8b
• Frequency (max): 12.58MHz
• Interface Type: I2C/SPI/UART
• Total Internal Ram Size: 2.25KB
• # I/os (max): 26
• Number Of Timers - General Purpose: 3
• Operating Supply Voltage (typ): 3.3/5V
• Operating Supply Voltage (max): 5.25V
• Operating Supply Voltage (min): 2.7V
• On-chip Adc: 2(2-chx16-bit)
• On-chip Dac: 1-chx12-bit
• Instruction Set Architecture: CISC
• Operating Temp Range: -40C to 125C
• Operating Temperature Classification: Automotive
• Mounting: Surface Mount
• Pin Count: 52
• Package Type: MQFP
• Package: 52MQFP
• Family Name: ADuC8xx
• Maximum Speed: 12.58 MHz
• Operating Supply Voltage: 3.3|5 V
• Data Bus Width: 8 Bit
• Number Of Programmable I/os: 26
• Number Of Timers: 3
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Programming the Flash/EE Data Memory
A user wishes to program F3H into the second byte on Page 03H
of the Flash/EE data memory space while preserving the other
three bytes already in this page.
A typical program of the Flash/EE Data array will involve:
1. Setting EADRH/L with the page address
2. Writing the data to be programmed to the EDATA1–4
3. Writing the ECON SFR with the appropriate command
Step 1: Set Up the Page Address
The two address registers, EADRH and EADRL, hold the high
byte address and the low byte address of the page to be addressed.
The assembly language to set up the address may appear as:
Step 2: Set Up the EDATA Registers
The four values to be written into the page into the four SFRs
EDATA1–4. Since we do not know three of them, it is necessary
to read the current page and overwrite the second byte.
Step 3: Program Page
A byte in the Flash/EE array can be programmed only if it has
previously been erased. To be more specific, a byte can only be
programmed if it already holds the value FFH. Because of the
Flash/EE architecture, this erase must happen at a page level.
Therefore, a minimum of four bytes (1 page) will be erased when
an erase command is initiated. Once the page is erased, we can
program the four bytes in-page and then perform a verification of
the data.
Note that although the four Kbytes of Flash/EE data memory
is shipped from the factory pre-erased, i.e., Byte locations
REV. A
MOV EADRH,#0 ; Set Page Address Pointer
MOV EADRL,#03H
MOV ECON,#1 ; Read Page into EDATA1-4
MOV EDATA2,#0F3H ; Overwrite byte 2
MOV ECON,#5 ; ERASE Page
MOV ECON,#2 ; WRITE Page
MOV ECON,#4 ; VERIFY Page
MOV A,ECON ; Check if ECON=0 (OK!)
JNZ ERROR
–33–
set to FFH, it is nonetheless good programming practice to
include an erase-all routine as part of any configuration/setup
code running on the ADuC836. An ERASE-ALL command
consists of writing 06H to the ECON SFR, which initiates an
erase of the 4-Kbyte Flash/EE array.This command coded in
8051 assembly would appear as:
Flash/EE Memory Timing
Typical program and erase times for the ADuC836 are as follows:
Normal Mode (operating on Flash/EE data memory)
ULOAD Mode (operating on Flash/EE program memory)
It should be noted that a given mode of operation is initiated as
soon as the command word is written to the ECON SFR. The
core microcontroller operation on the ADuC836 is idled until the
requested Program/Read or Erase mode is completed.
In practice, this means that even though the Flash/EE memory
mode of operation is typically initiated with a two-machine
cycle MOV instruction (to write to the ECON SFR), the next
instruction will not be executed until the Flash/EE operation is
complete. This means that the core will not respond to interrupt
requests until the Flash/EE operation is complete, although the
core peripheral functions like counter/timers will continue to
count and time as configured throughout this period.
WRITEPAGE (4 bytes)
VERIFYPAGE (4 bytes)
WRITEBYTE (1 byte)
WRITEPAGE (256 bytes)
WRITEBYTE (1 byte)
MOV ECON,#06H ; Erase all Command
READPAGE (4 bytes)
ERASEPAGE (4 bytes)
ERASEALL (4 Kbytes)
READBYTE (1 byte)
ERASEPAGE (64 bytes)
ERASEALL (56 Kbytes)
; 2 ms Duration
– 5 machine cycles
– 380 s
– 5 machine cycles
– 2 ms
– 2 ms
– 3 machine cycles
– 200 s
– 15 ms
– 2 ms
– 2 ms
– 200 s
ADuC836