ADUC836BSZ Analog Devices Inc, ADUC836BSZ Datasheet - Page 72

• Manufacturer Part Number: ADUC836BSZ
• Description: 16bit Dual ADC With Embedded 8 Bit MCU
• Manufacturer: Analog Devices Inc
• Series: MicroConverter® ADuC8xxr

Specifications of ADUC836BSZ

• Core Processor: 8052
• Core Size: 8-Bit
• Speed: 12.58MHz
• Connectivity: EBI/EMI, I²C, SPI, UART/USART
• Peripherals: POR, PSM, PWM, Temp Sensor, WDT
• Number Of I /o: 34
• Program Memory Size: 62KB (62K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 4K x 8
• Ram Size: 2.25K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.25 V
• Data Converters: A/D 7x16b; D/A 1x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 52-MQFP, 52-PQFP
• Cpu Family: ADuC8xx
• Device Core: 8052
• Device Core Size: 8b
• Frequency (max): 12.58MHz
• Interface Type: I2C/SPI/UART
• Total Internal Ram Size: 2.25KB
• # I/os (max): 26
• Number Of Timers - General Purpose: 3
• Operating Supply Voltage (typ): 3.3/5V
• Operating Supply Voltage (max): 5.25V
• Operating Supply Voltage (min): 2.7V
• On-chip Adc: 2(2-chx16-bit)
• On-chip Dac: 1-chx12-bit
• Instruction Set Architecture: CISC
• Operating Temp Range: -40C to 125C
• Operating Temperature Classification: Automotive
• Mounting: Surface Mount
• Pin Count: 52
• Package Type: MQFP
• Package: 52MQFP
• Family Name: ADuC8xx
• Maximum Speed: 12.58 MHz
• Operating Supply Voltage: 3.3|5 V
• Data Bus Width: 8 Bit
• Number Of Programmable I/os: 26
• Number Of Timers: 3
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Parameter
EXTERNAL DATA MEMORY READ CYCLE
ADuC836
t
t
t
t
t
t
t
t
t
t
t
t
RLRH
AVLL
LLAX
RLDV
RHDX
RHDZ
LLDV
AVDV
LLWL
AVWL
RLAZ
WHLH
RD Pulsewidth
Address Valid after ALE Low
Address Hold after ALE Low
RD Low to Valid Data In
Data and Address Hold after RD
Data Float after RD
ALE Low to Valid Data In
Address to Valid Data In
ALE Low to RD Low
Address Valid to RD Low
RD Low to Address Float
RD High to ALE High
PORT 0 (I/O)
CORE_CLK
PORT 2 (O)
PSEN (O)
ALE (O)
RD (O)
t
AVLL
Figure 72. External Data Memory Read Cycle
A16–A23
A0–A7
(OUT)
t
AVDV
t
LLAX
t
AVWL
t
LLWL
Min
377
39
44
0
188
188
39
12.58 MHz Core_Clk
t
LLDV
–72–
t
RLAZ
t
RLDV
A8–A15
Max
232
89
486
550
288
0
119
t
DATA (IN)
RLRH
t
RHDX
Min
6t
t
t
0
3t
4t
t
CORE
CORE
CORE
CORE
CORE
CORE
– 40
– 35
– 40
Variable Core_Clk
– 100
– 50
– 130
t
WHLH
t
RHDZ
Max
5t
2t
8t
9t
3t
0
t
CORE
CORE
CORE
CORE
CORE
CORE
+ 40
– 165
– 70
– 150
– 165
+ 50
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
REV. A