ADUC836BSZ Analog Devices Inc, ADUC836BSZ Datasheet - Page 79

• Manufacturer Part Number: ADUC836BSZ
• Description: 16bit Dual ADC With Embedded 8 Bit MCU
• Manufacturer: Analog Devices Inc
• Series: MicroConverter® ADuC8xxr

Specifications of ADUC836BSZ

• Core Processor: 8052
• Core Size: 8-Bit
• Speed: 12.58MHz
• Connectivity: EBI/EMI, I²C, SPI, UART/USART
• Peripherals: POR, PSM, PWM, Temp Sensor, WDT
• Number Of I /o: 34
• Program Memory Size: 62KB (62K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 4K x 8
• Ram Size: 2.25K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.25 V
• Data Converters: A/D 7x16b; D/A 1x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 52-MQFP, 52-PQFP
• Cpu Family: ADuC8xx
• Device Core: 8052
• Device Core Size: 8b
• Frequency (max): 12.58MHz
• Interface Type: I2C/SPI/UART
• Total Internal Ram Size: 2.25KB
• # I/os (max): 26
• Number Of Timers - General Purpose: 3
• Operating Supply Voltage (typ): 3.3/5V
• Operating Supply Voltage (max): 5.25V
• Operating Supply Voltage (min): 2.7V
• On-chip Adc: 2(2-chx16-bit)
• On-chip Dac: 1-chx12-bit
• Instruction Set Architecture: CISC
• Operating Temp Range: -40C to 125C
• Operating Temperature Classification: Automotive
• Mounting: Surface Mount
• Pin Count: 52
• Package Type: MQFP
• Package: 52MQFP
• Family Name: ADuC8xx
• Maximum Speed: 12.58 MHz
• Operating Supply Voltage: 3.3|5 V
• Data Bus Width: 8 Bit
• Number Of Programmable I/os: 26
• Number Of Timers: 3
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Parameter
I
*Input filtering on both the SCLOCK and SDATA inputs surpresses noise spikes less than 50 ns.
REV. A
2
C-SERIAL INTERFACE TIMING
t
t
t
t
t
t
t
t
t
t
t
L
H
SHD
DSU
DHD
RSU
PSU
BUF
R
F
SUP
*
SDATA (I/O)
SCLK (I)
t
PSU
SCLOCK Low Pulsewidth
SCLOCK High Pulsewidth
Start Condition Hold Time
Data Setup Time
Data Hold Time
Setup Time for Repeated Start
Stop Condition Setup Time
Bus Free Time between a STOP
Condition and a START Condition
Rise Time of Both SCLOCK and SDATA
Fall Time of Both SCLOCK and SDATA
Pulsewidth of Spike Suppressed
CONDITION
STOP
PS
t
BUF
CONDITION
START
t
DSU
t
SHD
Figure 79. I
MSB
1
t
DHD
2
C Compatible InterfaceTiming
2-7
–79–
t
L
LSB
8
t
SUP
Min
4.7
4.0
0.6
100
0.6
0.6
1.3
t
H
t
DSU
t
SUP
ACK
9
t
RSU
Max
0.9
300
300
50
t
DHD
REPEATED
START
S(R)
t
F
MSB
t
F
1
t
R
t
R
ADuC836
Unit
µs
µs
µs
ns
µs
µs
µs
µs
ns
ns
ns