ADUC836BSZ Analog Devices Inc, ADUC836BSZ Datasheet - Page 53

16bit Dual ADC With Embedded 8 Bit MCU

ADUC836BSZ

Manufacturer Part Number
ADUC836BSZ
Description
16bit Dual ADC With Embedded 8 Bit MCU
Manufacturer
Analog Devices Inc
Series
MicroConverter® ADuC8xxr
Datasheet

Specifications of ADUC836BSZ

Core Processor
8052
Core Size
8-Bit
Speed
12.58MHz
Connectivity
EBI/EMI, I²C, SPI, UART/USART
Peripherals
POR, PSM, PWM, Temp Sensor, WDT
Number Of I /o
34
Program Memory Size
62KB (62K x 8)
Program Memory Type
FLASH
Eeprom Size
4K x 8
Ram Size
2.25K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.25 V
Data Converters
A/D 7x16b; D/A 1x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Package / Case
52-MQFP, 52-PQFP
Cpu Family
ADuC8xx
Device Core
8052
Device Core Size
8b
Frequency (max)
12.58MHz
Interface Type
I2C/SPI/UART
Total Internal Ram Size
2.25KB
# I/os (max)
26
Number Of Timers - General Purpose
3
Operating Supply Voltage (typ)
3.3/5V
Operating Supply Voltage (max)
5.25V
Operating Supply Voltage (min)
2.7V
On-chip Adc
2(2-chx16-bit)
On-chip Dac
1-chx12-bit
Instruction Set Architecture
CISC
Operating Temp Range
-40C to 125C
Operating Temperature Classification
Automotive
Mounting
Surface Mount
Pin Count
52
Package Type
MQFP
Package
52MQFP
Family Name
ADuC8xx
Maximum Speed
12.58 MHz
Operating Supply Voltage
3.3|5 V
Data Bus Width
8 Bit
Number Of Programmable I/os
26
Number Of Timers
3
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

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TCON
SFR Address
Power-On Default Value
Bit Addressable
Bit
7
6
5
4
3
2
1
0
*These bits are not used in the control of Timer/Counter 0 and 1, but are used instead in the control and monitoring of the external INT0 and INT1 interrupt pins.
Timer/Counter 0 and 1 Data Registers
Both Timer 0 and Timer 1 consist of two 8-bit registers. These can be used as independent registers or combined to be a single 16-bit
register, depending on the timer mode configuration.
TH0 and TL0
Timer 0 high byte and low byte.
SFR Address = 8CH, 8AH, respectively.
TH1 and TL1
Timer 1 high byte and low byte.
SFR Address = 8DH, 8BH, respectively.
REV. A
Name
TF1
TR1
TF0
TR0
IE1*
IT1*
IE0*
IT0*
Description
Timer 1 Overflow Flag.
Set by hardware on a Timer/Counter 1 overflow.
Cleared by hardware when the Program Counter (PC) vectors to the interrupt service routine.
Timer 1 Run Control Bit.
Set by user to turn on Timer/Counter 1.
Cleared by user to turn off Timer/Counter 1.
Timer 0 Overflow Flag.
Set by hardware on a Timer/Counter 0 overflow.
Cleared by hardware when the PC vectors to the interrupt service routine.
Timer 0 Run Control Bit.
Set by user to turn on Timer/Counter 0.
Cleared by user to turn off Timer/Counter 0.
External Interrupt 1 (INT1) Flag.
Set by hardware by a falling edge or zero level being applied to external interrupt pin INT1, depending on bit IT1 state.
Cleared by hardware when the PC vectors to the interrupt service routine only if the interrupt was transition-
activated. If level-activated, the external requesting source rather than the on-chip hardware, controls the request flag.
External Interrupt 1 (IE1) Trigger Type.
Set by software to specify edge-sensitive detection (i.e., 1-to-0 transition).
Cleared by software to specify level-sensitive detection (i.e., zero level).
External Interrupt 0 (INT0) Flag.
Set by hardware by a falling edge or zero level being applied to external interrupt pin INT0, depending on bit IT0 state.
Cleared by hardware when the PC vectors to the interrupt service routine only if the interrupt was transition-
activated. If level-activated, the external requesting source controls the request flag, rather than the on-chip hardware.
External Interrupt 0 (IE0) Trigger Type.
Set by software to specify edge-sensitive detection (i.e., 1-to-0 transition).
Cleared by software to specify level-sensitive detection (i.e., zero level).
Timer/Counter 0 and 1 Control Register
88H
00H
Yes
Table XXVII. TCON SFR Bit Designations
–53–
ADuC836

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