ADUC836BSZ Analog Devices Inc, ADUC836BSZ Datasheet - Page 38

• Manufacturer Part Number: ADUC836BSZ
• Description: 16bit Dual ADC With Embedded 8 Bit MCU
• Manufacturer: Analog Devices Inc
• Series: MicroConverter® ADuC8xxr

Specifications of ADUC836BSZ

• Core Processor: 8052
• Core Size: 8-Bit
• Speed: 12.58MHz
• Connectivity: EBI/EMI, I²C, SPI, UART/USART
• Peripherals: POR, PSM, PWM, Temp Sensor, WDT
• Number Of I /o: 34
• Program Memory Size: 62KB (62K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 4K x 8
• Ram Size: 2.25K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.25 V
• Data Converters: A/D 7x16b; D/A 1x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 52-MQFP, 52-PQFP
• Cpu Family: ADuC8xx
• Device Core: 8052
• Device Core Size: 8b
• Frequency (max): 12.58MHz
• Interface Type: I2C/SPI/UART
• Total Internal Ram Size: 2.25KB
• # I/os (max): 26
• Number Of Timers - General Purpose: 3
• Operating Supply Voltage (typ): 3.3/5V
• Operating Supply Voltage (max): 5.25V
• Operating Supply Voltage (min): 2.7V
• On-chip Adc: 2(2-chx16-bit)
• On-chip Dac: 1-chx12-bit
• Instruction Set Architecture: CISC
• Operating Temp Range: -40C to 125C
• Operating Temperature Classification: Automotive
• Mounting: Surface Mount
• Pin Count: 52
• Package Type: MQFP
• Package: 52MQFP
• Family Name: ADuC8xx
• Maximum Speed: 12.58 MHz
• Operating Supply Voltage: 3.3|5 V
• Data Bus Width: 8 Bit
• Number Of Programmable I/os: 26
• Number Of Timers: 3
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Mode 4: Dual NRZ 16-Bit - DAC
Mode 4 provides a high speed PWM output similar to that of a
- DAC. Typically, this mode will be used with the PWM clock
equal to 12.58 MHz.
In this mode, P1.0 and P1.1 are updated every PWM clock
(80 ns in the case of 12.58 MHz). Over any 65536 cycles (16-bit
PWM), PWM0 (P1.0) is high for PWM0H/L cycles and low for
(65536 – PWM0H/L) cycles. Similarly, PWM1 (P1.1) is high for
PWM1H/L cycles and low for (65536 – PWM1H/L) cycles.
If PWM1H is set to 4010H (slightly above one quarter of FS),
then typically P1.1 will be low for three clocks and high for one
clock (each clock is approximately 80 ns). Over every 65536
clocks, the PWM will compromise for the fact that the output
should be slightly above one quarter of full scale by having a high
cycle followed by only two low cycles.
For faster DAC outputs (at lower resolution), write 0s to the
LSBs that are not required with a 1 in the LSB position. If, for
example, only 12-bit performance is required, write 0001 to the
4 LSBs.This means that a 12-bit accurate - DAC output can
occur at 3 kHz. Similarly, writing 00000001 to the 8 LSBs gives
an 8-bit accurate - DAC output at 49 kHz.
Mode 5: Dual 8-Bit PWM
In Mode 5, the duty cycle of the PWM outputs and the resolution
of the PWM outputs are individually programmable. The max-
imum resolution of the PWM output is 8 bits.
The output resolution is set by the PWM1L and PWM1H SFRs
for the P1.0 and P1.1 outputs, respectively. PWM0L and
PWM0H set the duty cycles of the PWM outputs at P1.0 and
P1.1, respectively. Both PWMs have the same clock source and
clock divider.
ADuC836
12.583MHz
PWM0H/L = C000H
PWM1H/L = 4000H
16-BIT
16-BIT
16-BIT
16-BIT
Figure 30. PWM Mode 4
LATCH
CARRY OUT AT P1.0
CARRY OUT AT P1.1
16-BIT
16-BIT
80s
80s
0
0
1
0
1
0
1
1
0
0
0
1
1
0
–38–
Mode 6: Dual RZ 16-Bit - DAC
Mode 6 provides a high speed PWM output similar to that of a
- DAC. Mode 6 operates very similarly to Mode 4. However,
the key difference is that Mode 6 provides return to zero (RZ)
- DAC output. Mode 4 provides non-return-to-zero -
DAC outputs. The RZ mode ensures that any difference in the
rise and fall times will not affect the - DAC INL. However,
the RZ Mode halves the dynamic range of the - DAC outputs
from 0AV
be used with a PWM clock divider of 4.
If PWM1H is set to 4010H (slightly above one quarter of FS)
then P1.1 will typically be low for three full clocks (3  80 ns),
high for half a clock (40 ns) and then low again for half a clock
(40 ns) before repeating itself. Over every 65536 clocks, the
PWM will compromise for the fact that the output should be
slightly above one quarter of full scale by leaving the output high
for two half clocks in four every so often.
For faster DAC outputs (at lower resolution), write 0s to the
LSBs that are not required with a 1 in the LSB position. If, for
example, only 12-bit performance is required, write 0001 to the
4 LSBs.This means that a 12-bit accurate - DAC output can
occur at 3 kHz. Similarly, writing 00000001 to the 8 LSBs gives
an 8-bit accurate - DAC output at 49 kHz.
PWM0H/L = C000H
PWM1H/L = 4000H
3.146MHz
16-BIT
16-BIT
16-BIT
16-BIT
DD
to 0AV
Figure 32. PWM Mode 6
Figure 31. PWM Mode 5
LATCH
PWM COUNTERS
DD
CARRY OUT AT P1.0
/2. For best results, this mode should
CARRY OUT AT P1.1
16-BIT
16-BIT
318s
318s
0 1
0
0
1
0 1
1
PWM1L
PWM1H
PWM0L
PWM0H
P1.1
0
P1.0
0
0
1
0
REV. A
1
0