ADUC836BSZ Analog Devices Inc, ADUC836BSZ Datasheet - Page 70

• Manufacturer Part Number: ADUC836BSZ
• Description: 16bit Dual ADC With Embedded 8 Bit MCU
• Manufacturer: Analog Devices Inc
• Series: MicroConverter® ADuC8xxr

Specifications of ADUC836BSZ

• Core Processor: 8052
• Core Size: 8-Bit
• Speed: 12.58MHz
• Connectivity: EBI/EMI, I²C, SPI, UART/USART
• Peripherals: POR, PSM, PWM, Temp Sensor, WDT
• Number Of I /o: 34
• Program Memory Size: 62KB (62K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 4K x 8
• Ram Size: 2.25K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.25 V
• Data Converters: A/D 7x16b; D/A 1x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 52-MQFP, 52-PQFP
• Cpu Family: ADuC8xx
• Device Core: 8052
• Device Core Size: 8b
• Frequency (max): 12.58MHz
• Interface Type: I2C/SPI/UART
• Total Internal Ram Size: 2.25KB
• # I/os (max): 26
• Number Of Timers - General Purpose: 3
• Operating Supply Voltage (typ): 3.3/5V
• Operating Supply Voltage (max): 5.25V
• Operating Supply Voltage (min): 2.7V
• On-chip Adc: 2(2-chx16-bit)
• On-chip Dac: 1-chx12-bit
• Instruction Set Architecture: CISC
• Operating Temp Range: -40C to 125C
• Operating Temperature Classification: Automotive
• Mounting: Surface Mount
• Pin Count: 52
• Package Type: MQFP
• Package: 52MQFP
• Family Name: ADuC8xx
• Maximum Speed: 12.58 MHz
• Operating Supply Voltage: 3.3|5 V
• Data Bus Width: 8 Bit
• Number Of Programmable I/os: 26
• Number Of Timers: 3
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

ADuC836
TIMING SPECIFICATIONS
Parameter
CLOCK INPUT (External Clock Driven XTAL1)
NOTES
1
2
3
4
5
6
AC inputs during testing are driven at DV
Logic 0, as shown in Figure 70.
For timing purposes, a port pin is no longer floating when a 100 mV change from load voltage occurs. A port pin begins to float when a 100 mV change from the loaded
V
C
ADuC836 internal PLL locks onto a multiple (384 times) the external crystal frequency of 32.768 kHz to provide a stable 12.583 MHz internal clock for the system.
The core can operate at this frequency or at a binary submultiple called Core_Clk, selected via the PLLCON SFR.
This number is measured at the default Core_Clk operating frequency of 1.57 MHz.
ADuC836 Machine Cycle Time is nominally defined as 12/Core_Clk.
OH
LOAD
t
t
t
t
t
1/t
t
t
CK
CKL
CKH
CKR
CKF
CORE
CYC
/V
CORE
OL
for Port 0, ALE, PSEN outputs = 100 pF; C
level occurs, as shown in Figure 70.
XTAL1 Period
XTAL1 Width Low
XTAL1 Width High
XTAL1 Rise Time
XTAL1 Fall Time
ADuC836 Core Clock Frequency
ADuC836 Core Clock Period
ADuC836 Machine Cycle Time
DV
DD
– 0.5V
0.45V
DD
– 0.5 V for a Logic 1, and 0.45 V for a Logic 0. Timing measurements are made at V
1, 2, 3
0.2DV
0.2DV
TEST POINTS
LOAD
Figure 70.Timing Waveform Characteristics
DD
DD
for all other outputs = 80 pF, unless otherwise noted.
– 0.1V
+ 0.9V
t
CKH
5
(AV
all specifications T
6
DD
4
= 2.7 V to 3.6 V or 4.75 V to 5.25 V, DV
Figure 69. XTAL1 Input
–70–
Min
0.098
0.95
t
V
MIN
CKL
LOAD
to T
V
V
32.768 kHz External Crystal
LOAD
LOAD
MAX
t
, unless otherwise noted.)
– 0.1V
+ 0.1V
CKR
t
CK
Typ
30.52
6.26
6.26
9
9
0.636
7.6
REFERENCE
POINTS
TIMING
DD
= 2.7 V to 3.6 V or 4.75 V to 5.25 V;
t
CKF
Max
12.58
122.45
IH
V
V
min for a Logic 1, and V
LOAD
LOAD
– 0.1V
+ 0.1V
V
LOAD
Unit
s
s
s
s
s
MHz
s
s
IL
max for a
REV. A