DS33Z11 Maxim Integrated Products, DS33Z11 Datasheet - Page 143

• Manufacturer Part Number: DS33Z11
• Description: Network Controller & Processor ICs Ethernet Mapper Ethe rnet-Serial TDM Ethe
• Manufacturer: Maxim Integrated Products

Specifications of DS33Z11

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

The DS33Z11 provides the TBSYNC signal as a byte boundary indication to an external interface when X.86
(LAPS) functionality is selected. The functional timing of TBSYNC is shown in the following figure. TBSYNC is
active high on the last bit of the byte being shifted out, and occurs every 8 bits. For the serial receiver interface,
RBSYNC is used to provide byte boundary indication to the DS33Z11 when X.86 (LAPS) mode is used. The
functional timing is shown in
shown in
Figure 10-3 Transmit Byte Sync Functional timing
Figure 10-4 Receive Byte Sync Functional Timing
10.2 MII and RMII Interfaces
The MII Interface Transmit Port has its own TX_CLK and data interface. The data TXD [3:0] operates
synchronously with TX_CLK. The LSB is presented first. TX_CLK should be 2.5 MHz for 10 Mbps operation and
25 MHz for 100 Mbps operation. TX_EN is valid at the same time as the first byte of the preamble. In DTE Mode
TX_CLK is input from the external PHY. In DCE Mode, the DS33Z11 provides TX_CLK, derived from an external
reference (SYSCLKI).
In Half-Duplex (DTE) Mode, the DS33Z11 supports CRS and COL signals. CRS is active when the PHY detects
transmit or receive activity. If there is a collision as indicated by the COL input, the DS33Z11 will replace the data
nibbles with jam nibbles. After a “random“ time interval, the packet is retransmitted. The MAC will try to send the
packet a maximum of 16 times. The jam sequence consists of 55555555h. Note that the COL signal and CRS
can be asynchronous to the TX_CLK and are only valid in half duplex mode.
RBYSYNC
TBYSYNC
RCLKI
TCLKI
RSER
TSER
Figure
10-4.
Figure
10-3. In X.86 Mode, the receiver expects the RBSYNC byte indicator as
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last bit
last bit
1st bit
1st bit