DS33Z11 Maxim Integrated Products, DS33Z11 Datasheet - Page 87

• Manufacturer Part Number: DS33Z11
• Description: Network Controller & Processor ICs Ethernet Mapper Ethe rnet-Serial TDM Ethe
• Manufacturer: Maxim Integrated Products

Specifications of DS33Z11

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Bits 3 – 5: Transmit Error Insertion Rate (TEIR[2:0]) These three bits indicate the rate at which errors are
inserted in the output data stream. One out of every 10
value of 0 disables error insertion at a specific rate. A TEIR[2:0] value of 1 result in every 10
TEIR[2:0] value of 2 results in every 100
with a TEIR[2:0] value that is non-zero. If this register is written to during the middle of an error insertion process,
the new error rate is started after the next error is inserted.
Bit 2: Bit Error Insertion Enable (BEI) When 0, single bit error insertion is disabled. When 1, single bit error
insertion is enabled.
Bit 1: Transmit Single Error Insert (TSEI) This bit causes a bit error to be inserted in the transmit data stream if
and single bit error insertion is enabled. A 0 to 1 transition causes a single bit error to be inserted. For a second
bit error to be inserted, this bit must be set to 0, and back to 1. Note: If this bit transitions more than once between
error insertion opportunities, only one error is inserted.
All other bits in this register besides BEI and TSEI and TIER must be reset to 0 for proper operation.
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Bit 3: Performance Monitoring Update Status (PMS) This bit indicates the status of the receive performance
monitoring register (counters) update. This bit will transition from low to high when the update is completed. PMS
is asynchronously forced low when the PMU bit goes low. TCLKI and RCLKI must be present.
Bit 1: Bit Error Count (BEC) When 0, the bit error count is zero. When 1, the bit error count is one or more.
Bit 0: Out Of Synchronization (OOS) When 0, the receive pattern generator is synchronized to the incoming
pattern. When 1, the receive pattern generator is not synchronized to the incoming pattern.
7
0
7
0
-
-
6
0
6
0
-
-
TEICR
Transmit Error Insertion Control Register
88h
BSR
BERT Status Register
8Ch
TIER2
th
5
0
5
0
-
bit being inverted. Error insertion starts when this register is written to
87 of 172
TIER1
4
0
4
0
-
n
bits is inverted. TEIR[2:0] is the value n. A TEIR[2:0]
TIER0
PMS
3
0
3
0
BEI
2
0
2
0
-
th
TSEI
BEC
bit being inverted. A
1
0
1
0
OOS
0
0
0
0
-