DS33Z11 Maxim Integrated Products, DS33Z11 Datasheet - Page 168

• Manufacturer Part Number: DS33Z11
• Description: Network Controller & Processor ICs Ethernet Mapper Ethe rnet-Serial TDM Ethe
• Manufacturer: Maxim Integrated Products

Specifications of DS33Z11

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

12.3 JTAG ID Codes
Table 12-2 ID Code Structure
12.4 Test Registers
IEEE 1149.1 requires a minimum of two test registers; the bypass register and the boundary scan register. An
optional test register has been included with the DS33Z11 design. This test register is the identification register
and is used in conjunction with the IDCODE instruction and the Test-Logic-Reset state of the TAP controller.
12.5 Boundary Scan Register
This register contains both a shift register path and a latched parallel output for all control cells and digital I/O
cells and is n bits in length.
12.6 Bypass Register
This is a single one-bit shift register used in conjunction with the BYPASS, CLAMP, and HIGHZ instructions,
which provides a short path between JTDI and JTDO.
12.7 Identification Register
The identification register contains a 32-bit shift register and a 32-bit latched parallel output. This register is
selected during the IDCODE instruction and when the TAP controller is in the Test-Logic-Reset state.
12.8 JTAG Functional Timing
This functional timing for the JTAG circuits shows:
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DS33Z11
DEVICE
The JTAG controller starting from reset state
Shifting out the first 4 LSB bits of the IDCODE
Shifting in the BYPASS instruction (111) while shifting out the mandatory X01 pattern
Shifting the TDI pin to the TDO pin through the bypass shift register
An asynchronous reset occurs while shifting
REVISION
ID[31:28]
0000
0000 0000 0110 0001
DEVICE CODE
ID[27:12]
168 of 172
MANUFACTURER’S CODE
000 1010 0001
ID[11:1]
REQUIRED
ID[0]
1