DS33Z11 Maxim Integrated Products, DS33Z11 Datasheet - Page 34

• Manufacturer Part Number: DS33Z11
• Description: Network Controller & Processor ICs Ethernet Mapper Ethe rnet-Serial TDM Ethe
• Manufacturer: Maxim Integrated Products

Specifications of DS33Z11

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

8.4 Resets and Low Power Modes
The external RST pin and the global reset bit in GL.CR1 create an internal global reset signal. The global reset
signal resets the status and control registers on the chip (except the
resets all the other flops to their reset values. The processor bus output signals are also placed in high-
impedance mode when the RST pin is active (low). The global reset bit
written to it, but is reset to zero when the external RST pin is active or when a zero is written to it. Allow 5
milliseconds after initiating a reset condition for the reset operation to complete.
The Serial Interface reset bit in LI.RSTPD resets all the status and control registers on the Serial interface to their
default values, except for the LI.RSTPD.RST bit. The Serial Interface includes the HDLC encoder/decoder, X86
encoder and decoder and the corresponding serial port. The Serial Interface reset bit (LI.RSTPD.RST) stays set
after a one is written to it, but is reset to zero when the global reset signal is active or when a zero is written to it.
If DS33Z11 is configured to use an external EEPROM, the DS33Z11 will provide the startup sequence to read the
device settings upon the rising edge of the external RST pin. When using the external EEPROM the device is
configured within 5 ms. This is dependent on an EEPROM clock of 8.33 MHz. The functional timing is provided by
Figure
Table 8-2 Reset Functions
RESET FUNCTION
Hardware Device Reset
Hardware JTAG Reset
Global Software Reset
Serial interface Reset
Queue Pointer Reset
There are several features in the DS33Z11 to reduce power consumption. The reset bit in the LI.RSTPD register
minimizes power usage in the Serial Interface. Additionally, the RST pin or GL.CR1.RST bit may be held in reset
indefinitely to keep the device in a low-power mode. Note that exiting a reset condition requires re-initialization
and configuration. For the lowest possible standby current, clocks may be externally gated.
10-10.
LOCATION
RST Pin
JTRST Pin
GL.CR1
LI.RSTPD
GL.C1QPR
34 of 172
COMMENTS
Transition from a logic 0 to a logic 1
resets the device.
Resets the JTAG test port.
Writing to this bit resets the device.
Writing to this bit resets the Serial
Interface.
Writing to this bit resets the Queue
Pointers
GL.CR1.
(GL.CR1.
RST bit) to their default values and
RST) stays set after a one is