DS33Z11 Maxim Integrated Products, DS33Z11 Datasheet - Page 47

• Manufacturer Part Number: DS33Z11
• Description: Network Controller & Processor ICs Ethernet Mapper Ethe rnet-Serial TDM Ethe
• Manufacturer: Maxim Integrated Products

Specifications of DS33Z11

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Table 8-6 MAC Control Registers
Table 8-7 MAC Status Registers
001Ch-001Fh
0008h-000Bh
0018h-001Bh
0000h-0003h
0004h-0007h
0014h-0017h
0100h-0103h
030Ch-030Fh
0308h-030Bh
0338h-033Bh
0200h-0203h
0204h-0207h
0300h-0303h
0334h-0337h
Address
Address
SU.MACCR
SU.MACAH
SU.MACAL
SU.MACMIIA
SU.MACMIID
SU.MACFCR
SU.MMCCTRL
SU.RxFrmCntr
SU.RxFrmOKCtr
SU.TxFrmCtr
SU.TxBytesCtr
SU.TxBytesOkCtr
SU.TxFrmUndr
SU.TxBdFrmsCtr
Register
Register
MAC Control Register. This register is used for
programming full duplex, half duplex, promiscuous mode,
and back-off limit for half duplex. The transmit and receive
enable bits must be set for the MAC to operate.
MAC Address High Register. This provides the physical
address for this MAC.
MAC Address Low Register. This provides the physical
address for this MAC.
MII Address Register. The address for PHY access
through the MDIO interface.
MII Data Register. Data to be written to (or read from) the
PHY through MDIO interface.
Flow Control Register
MMC Control Register bit 0 for resetting the status
counters
Register Description
47 of 172
All Frames Received counter
Number of Received Frames that are Good
Number of Frames Transmitted
Number of Bytes Transmitted
Number of Bytes Transmitted with good frames
Transmit FIFO underflow counter
Transmit Number of Frames Aborted
Register Description