DS33Z11 Maxim Integrated Products, DS33Z11 Datasheet - Page 25

• Manufacturer Part Number: DS33Z11
• Description: Network Controller & Processor ICs Ethernet Mapper Ethe rnet-Serial TDM Ethe
• Manufacturer: Maxim Integrated Products

Specifications of DS33Z11

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

SDMASK[0]
SDMASK[1]
SDMASK[2]
SDMASK[3]
SYSCLKI
SDCLKO
SDA[10]
SDA[11]
SDA[6]
SDA[7]
SDA[8]
SDA[9]
SBA[0]
SBA[1]
NAME
QOVF
SCAS
SDCS
SRAS
SWE
DS33Z11
CSBGA
PIN #
M10
(169)
G13
M5
M7
M8
M6
M4
M9
N8
N7
K6
H4
N6
G4
N5
C7
L9
L5
L6
DS33ZH1
BGA(100)
PIN #
K10
G5
G4
H5
G3
C5
H3
F8
F5
K4
F7
K3
F4
F3
E3
J4
J6
J3
—
1
(4mA)
TYPE
O
O
O
O
O
O
O
QUEUE STATUS
I
I
25 of 172
DS33Z11. No user programming for SDRAM buffering is
required.
SDRAM Bank Select: These two bits select 1 of 4 banks
for the read/write/precharge operations.
Note: All SDRAM operations are controlled entirely by the
DS33Z11. No user programming for SDRAM buffering is
required.
Active-Low SDRAM Row Address Strobe: Used to latch
the row address on rising edge of SDCLKO. It is used with
commands for Bank Activate, Precharge, and Mode
Register Write.
Active-Low SDRAM Column Address Strobe: Used to
latch the column address on the rising edge of SDCLKO.
It is used with commands for Bank Activate, Precharge,
and Mode Register Write.
Active-Low SDRAM Write Enable: This output enables
write operation and auto precharge.
SDRAM Mask 0 through 3: When high, a write is done
for that byte. The least significant byte is SDATA7 to
SDATA0. The most significant byte is SDATA31 to
SDATA24.
SDRAM CLK Out: System clock output to the SDRAM.
This clock is a buffered version of SYSCLKI.
System Clock In: 100MHz System Clock input to the
DS33Z11, used for internal operation. This clock is
buffered and provided at SDCLKO for the SDRAM
interface. The DS33Z11 also provides a divided version
output at the REF_CLKO pin. A clock supply with ±100
ppm frequency accuracy is suggested.
Active-Low SDRAM Chip Select: This output enables
SDRAM access.
Queue Overflow: This pin goes high when the transmit or
receive queue has overflowed. This pin goes low when the
high watermark is reached again. This pin functions in
both software and hardware mode.
FUNCTION