DS33Z11 Maxim Integrated Products, DS33Z11 Datasheet - Page 43

• Manufacturer Part Number: DS33Z11
• Description: Network Controller & Processor ICs Ethernet Mapper Ethe rnet-Serial TDM Ethe
• Manufacturer: Maxim Integrated Products

Specifications of DS33Z11

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

DS33Z11 Ethernet Mapper
8.13 ETHERNET Interface Port
The Ethernet port interface allows for direct connection to an Ethernet PHY. The interface consists of a 10/100
Mbps MII/RMII interface and an Ethernet MAC. In RMII operation, the interface contains 7 signals with a
reference clock of 50 MHz. In MII operation, the interface contains 17 signals and a clock reference of 25 MHz.
The DS33Z11 can be configured to RMII or MII interface by the Hardware pin RMIIMIIS. If the port is configured
for MII in DCE mode, REF_CLK must be 25 MHz. The DS33Z11 will internally generate the TX_CLK and
RX_CLK outputs (at 25 MHz for 100Mbps, 2.5 MHz for 10Mbps) required for DCE mode from the REF_CLK
input. In MII mode with DTE operation, the TX_CLK and RX_CLK signals are generated by the PHY and are
inputs to the DS33Z11. For more information on clocking the Ethernet Interface, see Section 8.3.
The data received from the MII or RMII interface is processed by the internal IEEE 802.3 compliant Ethernet
MAC. The user can select the maximum frame size (up to 2016 bytes) that is received with the SU.RMFSRH and
SU.RMFSRL registers. The maximum frame length (in bits) is the number specified in SU.RMFSRH and
SU.RMFSRL multiplied by 8. Any programmed value greater than 2016 bytes will result in unpredictable
behavior and should be avoided. The maximum frame size is shown in
Figure
8-4. The length includes only
destination address, source address, VLAN tag (2 bytes), type length field, data and CRC32. The frame size is
different than the 802.3 “type length field”.
Frames coming from the Ethernet PHY or received from the packet processor are rejected if greater than the
maximum frame size specified. Each Ethernet frame sent or received generates status bits (SU.TFSH and
SU.TFSL and SU.RFSB0 to SU.RFSB3). These are real time status registers and will change as each frame is
sent or received. Hence they are useful to the user only when one frame is sent or received and the status is
associated with the frame sent or received.
Figure 8-4 IEEE 802.3 Ethernet Frame
Type
Preamble
SFD
Destination Adrs
Source Address
Data
CRC32
Lenght
4
7
1
6
6
2
46-1500
Max Frame Length
The distant end will normally reject the sent frames if jabber timeout, Loss of carrier, excessive deferral, late
collisions, excessive collisions, under run, deferred or collision errors occur. Transmission of a frame under any of
theses errors will generate a status bit in SU.TFSL, SU.TFSH. The DS33Z11 provides user the option to
automatically retransmit the frame if any of the errors have occurred through the bit settings in SU.TFRC.
Deferred
frames
and
heartbeat
fail
have
separate
resend
control
bits
(SU.TFRC.TFBFCB
and
SU.TFRC.TPRHBC). If there is no carrier (indicated by the MAC Transmit Packet Status), the transmit queue
(data from the Serial Interface to the SDRAM to Ethernet Interface) can be selectively flushed. This is controlled
by SU.TFRC.NCFQ.
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