DS33Z11 Maxim Integrated Products, DS33Z11 Datasheet - Page 46

• Manufacturer Part Number: DS33Z11
• Description: Network Controller & Processor ICs Ethernet Mapper Ethe rnet-Serial TDM Ethe
• Manufacturer: Maxim Integrated Products

Specifications of DS33Z11

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Figure 8-6 DS33Z11 Configured as a DCE in MII Mode
8.14 Ethernet MAC
Indirect addressing is required to access the MAC register settings. Writing to the MAC registers requires the
SU.MACWD0-3 registers to be written with 4 bytes of data. The address must be written to SU.MACAWL and
SU.MACAWH. A write command is issued by writing a zero to SU.MACRWC.MCRW and a one to
SU.MACRWC.MCS (MAC command status). MCS is cleared by the DS33Z11 when the operation is complete.
Reading from the MAC registers requires the SU.MACRADH and SU.MACRADL registers to be written with the
address for the read operation. A read command is issued by writing a one to SU.MACRWC.MCRW and a zero
to SU.MACRWC.MCS. SU.MACRWC.MCS is cleared by the DS33Z11 when the operation is complete. After
MCS is clear, valid data is available in SU.MACRD0-SU.MACRD3. Note that only one operation can be initiated
(read or write) at one time. Data cannot be written or read from the MAC registers until the MCS bit has been
cleared by the device. The MAC Registers are detailed in the following table.
WAN
Arbiter
DS33Z11
DCE
MAC
Rx
Tx
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RXD[3:0]
TXD[3:0]
COL_DET
TX_CLK
RX_CRS
RX_ERR
RX_CLK
TX_EN
RXDV
MDIO
MDC
TX_EN
COL_DET
MDIO
TX_ERR
RX_CRS
RXD[3:0]
MDC
TX_CLK
RX_CLK
RXDV
TXD[3:0]
DTE
Tx
Rx
MAC