DS33Z11 Maxim Integrated Products, DS33Z11 Datasheet - Page 33

• Manufacturer Part Number: DS33Z11
• Description: Network Controller & Processor ICs Ethernet Mapper Ethe rnet-Serial TDM Ethe
• Manufacturer: Maxim Integrated Products

Specifications of DS33Z11

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

DS33Z11 Ethernet Mapper
8.3.1 Serial Interface Clock Modes
The Serial Interface timing is determined by the line clocks. Both the transmit and receive clocks (TCLKI and
RCLKI) are inputs, and can be gapped.
8.3.2 Ethernet Interface Clock Modes
The Ethernet PHY interface has several different clocking requirements, depending on the mode of operation.
Table 8-1
outlines the possible clocking modes for the Ethernet Interface. The buffered REF_CLKO output is
generated by division of the 100 MHz system clock input by the user on SYSCLKI. The frequency of the
REF_CLKO pin is automatically determined by the DS33Z11 based on the state of the RMIIMIIS pin. The
REF_CLKO function can be turned off with the GL.CR1.RFOO bit.
In RMII mode, receive and transmit timing is always synchronous to a 50 MHz clock input on the REF_CLK pin.
The source of REF_CLK is expected to be the external PHY. More information on RMII mode can be found in
Section 8.14.2.
While using MII mode with DTE operation, the MII clocks (RX_CLK and TX_CLK) are inputs that are expected to
be provided by the external PHY. While using MII mode with DCE operation, the MII clocks (TX_CLK and
RX_CLK) are output by the DS33Z11, and are derived from the 25 MHz REF_CLK input. Note that in DCE and
RMII operating modes, the REF_CLKO signal should not be used to provide an input to REF_CLK, due to the
reset requirements in these operating modes. More information on MII mode can be found in Section 8.14.1.
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