DS33Z11 Maxim Integrated Products, DS33Z11 Datasheet - Page 84

• Manufacturer Part Number: DS33Z11
• Description: Network Controller & Processor ICs Ethernet Mapper Ethe rnet-Serial TDM Ethe
• Manufacturer: Maxim Integrated Products

Specifications of DS33Z11

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

9.4 BERT Registers
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Bit 7: This bit must be kept low for proper operation.
Bit 6: Performance Monitoring Update (PMU) This bit causes a performance monitoring update to be initiated.
A 0 to 1 transition causes the performance monitoring registers to be updated with the latest data, and the
counters reset (0 or 1). For a second performance monitoring update to be initiated, this bit must be set to 0, and
back to 1. If PMU goes low before the PMS bit goes high, an update might not be performed.
Bit 5: Receive New Pattern Load (RNPL) A zero to one transition of this bit will cause the programmed test
pattern (QRSS, PTS, PLF [4:0}, PTF [4:0], and BSP [31:0]) to be loaded in to the receive pattern generator. This
bit must be changed to zero and back to one for another pattern to be loaded. Loading a new pattern will forces
the receive pattern generator out of the “Sync” state which causes a resynchronization to be initiated. Note:
QRSS, PTS, PLF [4:0}, PTF [4:0], and BSP [31:0] must not change from the time this bit transitions from 0 to 1
until four RCLKI clock cycles after this bit transitions from 0 to 1.
Bit 4: Receive Pattern Inversion Control (RPIC) When 0, the receive incoming data stream is not altered.
When 1, the receive incoming data stream is inverted.
Bit 3: Manual Pattern Resynchronization (MPR) A zero to one transition of this bit will cause the receive
pattern generator to resynchronize to the incoming pattern. This bit must be changed to zero and back to one for
another resynchronization to be initiated. Note: A manual resynchronization forces the receive pattern generator
out of the “Sync” state.
Bit 2: Automatic Pattern Resynchronization Disable (APRD) When 0, the receive pattern generator will
automatically resynchronize to the incoming pattern if six or more times during the current 64-bit window the
incoming data stream bit and the receive pattern generator output bit did not match. When 1, the receive pattern
generator will not automatically resynchronize to the incoming pattern. Note: Automatic synchronization is
prevented by not allowing the receive pattern generator to automatically exit the “Sync” state.
Bit 1: Transmit New Pattern Load (TNPL) A zero to one transition of this bit will cause the programmed test
pattern (QRSS, PTS, PLF[4:0}, PTF[4:0], and BSP[31:0]) to be loaded in to the transmit pattern generator. This bit
must be changed to zero and back to one for another pattern to be loaded. Note: QRSS, PTS, PLF[4:0}, PTF[4:0],
and BSP[31:0] must not change from the time this bit transitions from 0 to 1 until four TCLKI clock cycles after this
bit transitions from 0 to 1.
Bit 0: Transmit Pattern Inversion Control (TPIC) When 0, the transmit outgoing data stream is not altered.
When 1, the transmit outgoing data stream is inverted.
7
0
-
PMU
6
0
BCR
BERT Control Register
80h
RNPL
5
0
84 of 172
RPIC
4
0
MPR
3
0
APRD
2
0
TNPL
1
0
TPIC
0
0