LAN91C100FD-ST SMSC, LAN91C100FD-ST Datasheet - Page 11

• Manufacturer Part Number: LAN91C100FD-ST
• Description: Ethernet ICs Non-PCI 10/100 Ethernet MAC
• Manufacturer: SMSC
• Type: Single Chip MAC and PHY Controllerr

Specifications of LAN91C100FD-ST

• Ethernet Connection Type: 10 Base-T, 100 Base-TX
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Product: Ethernet Controllers
• Number Of Transceivers: 1
• Standard Supported: 802.3
• Data Rate: 10 MB, 100 MB
• Supply Voltage (max): 7 V
• Supply Voltage (min): 0.3 V
• Supply Current (max): 40 mA
• Maximum Operating Temperature: + 70 C
• Package / Case: TQFP-208
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

SMSC LAN91C100FD Rev. D
FEAST Fast Ethernet Controller with Full Duplex Capability
PQFP/TQFP
20, 21, 22,
PIN NO.
Buffer Types
O4
O12
O16
O24
OD16
198
196
192
24
11
37
7
8
Receive
Data
Manage-
ment Data
Input
Manage-
ment Data
Output
Manage-
ment
Clock
Receive
Error
nChip
Select
Output
nReceive
Packet
Discard
NAME
Output buffer with 2mA source and 4mA sink
Output buffer with 6mA source and 12mA sink
Output buffer with 8mA source and 16mA sink
Output buffer with 12mA source and 24mA sink
Open drain buffer with 16mA sink
RXD0-
RXD3
MDI
MDO
MCLK
RX_ER
nCSOUT
nRXDISC
RDMAH
SYMBOL
DATASHEET
BUFFER
pulldown
pulldown
pullup
TYPE
I with
I with
I with
O4
O4
O4
O4
I
Page 11
Inputs. Received Data nibble from MII PHY.
These pins are ignored when MIISEL is low.
MII management data input.
MII management data output.
MII management clock.
Input. Indicates a code error detected by PHY.
Used by the LAN91C100FD to discard the
packet being received. The error indication
reported for this event is the same as a bad CRC
(Receive Status Word bit 13). This pin is
ignored when MIISEL is low.
Output. Chip Select provided for mapping of
PHY functions into LAN91C100FD decoded
space. Active on accesses to LAN91C100FD’s
eight lower addresses when the BANK
SELECTED is 7.
Input. Used to discard the receive packet being
stored in memory. Assertion of the pin during a
packet reception results in the interruption of
packet reception into memory. The memory
allocated to the packet and the packet number in
use are freed. The input is driven
asynchronously and is synchronized internally by
the LAN91C100FD. Pin assertion may take
place at any time during the receive DMA
packet. The assertion has no effect if there is no
packet being DMAed to memory or if asserted
during the last DMA write to memory. Works for
both MII and ENDEC. The typical use of
nRXDISC is with the LAN91C100FD in PRMS
mode with an external associative memory use
for address filtering. *Note: The pin must be
asserted for a minimum of 80ns.
Output. Active when the first dword of the
address is written (RCVDMA=1, RA10-RA4=0,
RA3-RA2=X).
DESCRIPTION
Revision 1.0 (09-22-08)